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SGU02G72H1BG2SA-BBRT Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part # SGU02G72H1BG2SA-BBRT
Description  2048MB DDR3 ??SDRAM Ultra Low Profile ECC DIMM
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SGU02G72H1BG2SA-BBRT Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

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Data Sheet
Rev.1.0
04.02.2011
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 03 03
www.swissbit.com
Page 2
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 03 15
eMail: info@swissbit.com
of 15
This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-
saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I
2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
DDR3 SDRAMs used
Row
Addr.
Device Bank
Addr.
Column
Addr.
Refresh
Module
Bank Select
256M x 72bit
18 x 128M x 8bit (1024Mbit)
14
BA0, BA1, BA2
10
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 17.75 (high) x 4.00 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SGU02G72H1BG2SA-BBRT
2048 MB
8.5 GB/s
1.87ns/1066MT/s
7-7-7
SGU02G72H1BG2SA-CCRT
2048 MB
10.6 GB/s
1.5ns/1333MT/s
9-9-9
Pin Name
A0
– A9, A11, A13
Address Inputs
A10/AP
Address Input / Autoprecharge Bit
A12/BC#
Address Input / Burst chop
BA0
– BA2
Bank Address Inputs
DQ0
– DQ63
Data Input / Output
CB0
– CB7
ECC check bits
DM0
– DM8
Input Data Mask
DQS0
– DQS8
Data Strobe, positive line
DQS0# - DQS8#
Data Strobe, negative line (only used when differential data strobe mode is enabled)
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
CKE0
– CKE1
Clock Enable
S0#, S1#
Chip Select
CK0
– CK1
Clock Inputs, positive line
Figure 1: Mechanical Dimensions


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