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LMP7312MAXNOPB Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LMP7312MAXNOPB Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 29 page IOL 100 PA IOH 100 PA VIO/2 TO SDO PIN CL 20 pF LMP7312 SNOSB32B – MARCH 2010 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (Serial Interface) (1) Unless otherwise specified. All limits ensured for TA = 25°C, V + = 5V, V− = 0V, 2.7V < V IO < 5.5V Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units VIL Input Logic Low Threshold 0.8 V VIH Input Logic High Threshold (SDO pin) 2 V VOL Output logic Low Threshold (SDO pin) ISDO= 100µA 0.2 V ISDO= 2mA 0.4 VOH Output logic High Threshold ISDO= 100µA VIO-0.2 V ISDO= 2mA VIO-0.6 t1 High Period, SCK (4) 100 ns t2 Low Period, SCK (4) 100 ns t3 Set Up Time, CS to SCK (4) 50 ns t4 Set Up Time, SDI to SCK (4) 30 ns t5 Hold Time, SCK to SDI (4) 10 ns t6 Prop. Delay, SCK to SDO (4) 60 ns t7 Hold Time, SCK Transition to CS Rising (4) 50 ns Edge t8 CS Inactive (4) 100 ns t9 Hold Time, SCK Transition to CS Falling (4) 10 ns Edge tR/tF Signal Rise and Fall Times (4) 1.5 5 ns (1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. (2) All limits are specified by testing, design, or statistical analysis. (3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. (4) Load for these tests is shown in Test Circuit Diagram. TEST CIRCUIT DIAGRAM 6 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LMP7312 |
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