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SGU01G64A1BG1SA-CCR Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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SGU01G64A1BG1SA-CCR Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
2 / 16 page Data Sheet Rev.1.1 11.04.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 16 This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module (UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power- saving “power-down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM using the standard I 2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR3 SDRAMs used Row Addr. Device Bank Addr. Column Addr. Refresh Module Bank Select 128M x 64bit 8 x 128M x 8bit (1024Mbit) 14 BA0, BA1, BA2 10 8k S0# Module Dimensions in mm 133.35 (long) x 30(high) x 2.70[max] (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SGU01G64A1BG1SA-BBR 1024 MB 8.5 GB/s 1.87ns/1066MT/s 7-7-7 SGU01G64A1BG1SA-CCR 1024 MB 10.6 GB/s 1.5ns/1333MT/s 9-9-9 SGU01G64A1BG1SA-DCR 1024 MB 12.8 GB/s 1.25ns/1600MT/s 11-11-11 Pin Name A0 – A9, A11 – A13 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 – BA2 Bank Address Inputs DQ0 – DQ63 Data Input / Output DM0 – DM7 Input Data Mask DQS0 – DQS7 Data Strobe, positive line DQS0# - DQS7# Data Strobe, negative line (only used when differential data strobe mode is enabled) S0# Chip Select RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0 Clock Enable Figure 1: Mechanical Dimensions |
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