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SGP04G72A1BD1SA-DCRT Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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SGP04G72A1BD1SA-DCRT Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 17 page Preliminary Data Sheet Rev.0.9 16.01.2014 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 9 CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) AC CHARACTERISTICS 12800 CL11 10600 CL9 PARAMETER SYMBOL MIN MAX MIN MAX Unit Clock cycle time CL = 11 tCK (11) 1.25 1.5 - - ns CL = 10 tCK (10) 1.5 <1.875 1.5 <1.875 ns CL = 9 tCK (9) 1.5 <1.875 1.5 <1.875 ns CL = 8 tCK (8) 1.875 <2.5 1.875 <2.5 ns CL = 7 tCK (7) 1.875 <2.5 1.875 <2.5 ns CL = 6 tCK (6) 2.5 3.3 2.5 3.3 ns CL = 5 tCK (5) 3.0 3.3 3.0 3.3 ns Read CMD to 1 st data tAA 13.75 - 13.5 - ns CK high-level width tCH (avg) 0.47 0.53 0.47 0.53 tCK CK low-level width tCL (avg) 0.47 0.53 0.47 0.53 tCK Data-out high-impedance window from CK/CK# tHZ - 225 - 250 ns Data-out low-impedance window from CK/CK# tLZ -450 225 -500 250 ns DQ and DM input pulse width ( for each input ) tDIPW 360 - 400 - ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH 0.38 - 0.38 - tCK (AVG) DQS input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK DQS input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK DQS read preamble tRPRE 0.9 Note 1 0.9 Note 1 tCK DQS read postamble tRPST 0.3 Note 2 0.3 Note 2 tCK DQS write preamble tWPRE 0.9 - 0.9 - tCK DQS write postamble tWPST 0.3 - 0.3 - tCK 1 The maximum preamble is bound by tLZDQS (MAX) 2 The maximum postamble is bound by tHZDQS (MAX) The DQ, DQS setup and hold times as well as Command/Address setup and hold times need to be calculated using the respective component data sheets with derating tables and the driver slew rate in combination with the JEDEC min/max routing information |
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