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R20UT2452EJ0110 Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # R20UT2452EJ0110
Description  E1/E20 Emulator
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R20UT2452EJ0110 Datasheet(HTML) 8 Page - Renesas Technology Corp

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E1/E20 Emulator
2. Designing the User System
R20UT2452EJ0110 Rev.1.10
Page 8 of 21
Mar 20, 2014
Caution】Wiring patterns between the connector and the MCU must be as short as possible
Figure 2-2 Recommended Circuit (debugging(LPD4pin) and programming(2wireUART))
or
Recommended Circuit (Only debugging(LPD4pin))
[Note1] This circuit is designed assuming that RESET signal is output from the N-ch open-drain buffer. For details, refer to 2.3.2.
[Note2] This signal must be set at low level when resetting.
In case of using general port, it is necessary to carry out circuit design so that it may not be driven to a High level from the
exterior when releasing of reset.
[Note3] Pin name differs according to the data sheet of MCU.
Refer to those the data sheet of MCU to find an actual pin name.
[Note4] Add a grounded guard ring to the pattern between the connector and the MCU.
Do not arrange these signal lines in parallel with or across other high-speed signal lines.
LPDCLK / FPCK
GND
FPMD0
LPDO / FPDT
FPDR/LPDIO
TVDD
LPDCLKOUT
GND
RESET_OUT
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
E1/E20 14pin
JP0_2(LPDCLK / FPCK)
FLMD0
JP0_1(LPDO / FPDT)
JP0_0(LPDIO / FPDR)
JP0_5(LPDCLKOUT)
P10_8(FLMD1)
RESET
Reset Circuit
Target device
EVCC
[Note1]
[Note1]
Emulator connector
[Note3]
1K ~10KΩ
100KΩ or more
[Note2]
[Note4]
[Note4]


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