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SDU12864H1B62MT-50R Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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SDU12864H1B62MT-50R Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 12 page Data Sheet Rev.1.1 18.09.2008 Swissbit Germany AG Wolfener Straße 36 Fon: +49 (0) 30 93 69 54 - 0 www.swissbit-germany.com Page 7 D-12681 Berlin Fax: +49 (0) 30 93 69 54 - 55 eMail: firma@swissbit-germany.com of 12 IDD Specifications AND CONDITIONS (0°C ≤ TA ≤ + 70°C ; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9 max. Parameter & Test Condition Symb. 3200-3033 2700-2533 2100-2533 Unit OPERATING CURRENT *) : One device bank; Active- Precharge; tRC= tRC (Min); tCK = tCK (Min); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDDO 1280 1080 960 mA OPERATING CURRENT :*) One device bank; Active-Read-Precharge; Burst = 2; tRC= tRC (Min); tCK = tCK (Min);IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 1520 1320 1200 mA PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (Min); CKE = (LOW) IDD2P 80 80 80 mA IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK (Min); CKE= HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F 880 720 640 mA ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (Min);CKE = LOW IDD3P 720 560 480 mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC= tRAS (Max); tCK = tCK (Min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 960 800 720 mA OPERATING CURRENT: Burst = 2; Reads; Continous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (Min); IOUT = 0mA IDD4R 3040 2640 2320 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (Min); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 3120 2800 2160 mA tRC = tRC (Min) IDD5 5520 4640 4480 mA AUTO REFRESH CURRENT tRC = 7.8125µs IDD6 176 160 160 mA SELF REFRESH CURRENT: CKE ≤ 0.2V IDD7 80 80 80 mA OPERATING CURRENT*): Four device bank interleaving READs (BL =4) with auto precharge, tRC = tRC (Min); tCK = tCK (Min); Address and control inputs change only during Active READ, or WRITE commands IDD8 3640 3280 2840 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. |
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