4

3704BX–DFLASH–11/2012

AT25BCM512B [Preliminary]

4.

Memory Array

To provide the greatest flexibility, the memory array of the AT25BCM512B can be erased in

three levels of granularity including a full chip erase. The size of the erase blocks is optimized for

both code and data storage applications, allowing both code and data segments to reside in

their own erase regions. The Memory Architecture Diagram illustrates the breakdown of each

erase level.

Figure 4-1.

Memory Architecture Diagram