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NIPXI-6232 Datasheet(PDF) 10 Page - National Instruments Corporation |
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NIPXI-6232 Datasheet(HTML) 10 Page - National Instruments Corporation |
10 / 14 page 10/14 www.ni.com NI 6232 (source output) Open to close 0.45 μs Close to open 2.15 μs NI 6233 (sink output) Open to close 0.4 μs Close to open 0.4 μs General-Purpose Counter/Timers Number of counter/timers 2 Resolution 32 bits Counter measurements Edge counting, pulse, semi-period, period, two-edge separation Position measurements X1, X2, X4 quadrature encoding with Channel Z reloading; two-pulse encoding Output applications Pulse, pulse train with dynamic updates, frequency division,equivalent time sampling Internal base clocks 80 MHz, 20 MHz, 0.1 MHz External base clock frequency 0 MHz to 20 MHz Base clock accuracy 50 ppm Inputs Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down Routing options for inputs Any input PFI, RTSI, PXI_TRIG, PXI_STAR, many internal signals FIFO 2 samples Data transfers Dedicated scatter-gather DMA controller for each counter/timer; interrupts; programmed I/O Frequency Generator Number of channels 1 Base clocks 10 MHz, 100 kHz Divisors 1 to 16 Base clock accuracy 50 ppm Output can be available on any output PFI or RTSI terminal. Phase-Locked Loop (PLL) Number of PLLs 1 Reference signal PXI_STAR, PXI_CLK10, RTSI <0..7> Output of PLL 80 MHz Timebase; other signals derived from 80 MHz Timebase including 20 MHz and 100 kHz Timebases External Digital Triggers Source Any input PFI, RTSI, PXI_TRIG, PXI_STAR Polarity Software-selectable for most signals Analog input function Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Convert Clock, Sample Clock Timebase Analog output function Start Trigger, Pause Trigger, Sample Clock, Sample Clock Timebase Counter/timer functions Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down Device-to-Device Trigger Bus PCI devices RTSI <0..7>1 PXI devices PXI_TRIG <0..7>, PXI_STAR Output selections 10 MHz Reference Clock; frequency generator output; many internal signals Debounce filter settings 125 ns, 6.425 μs, 2.54 ms, disabled; high and low transitions selectable per input 1 In other sections of this document, refers to RTSI <0..7> for PCI devices or PXI_TRIG <0..7> for PXI devices. RTSI Bus Interface PCI or PXI 3.3 V or 5 V signal environment |
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