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MT36VDDF25672Y-40B Datasheet(PDF) 5 Page - Micron Technology |
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MT36VDDF25672Y-40B Datasheet(HTML) 5 Page - Micron Technology |
5 / 20 page PDF: 09005aef80772fd2/Source: 09005aef8075ebf6 Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF36C128_256x72.fm - Rev. G 9/08 EN 5 ©2002 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the internal clock, input buffers, and output drivers. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. S0#, S1# Input Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data transfer to and from the module. CB0–CB7 I/O Check bits. DQ0–DQ63 I/O Data input/output: Data bus. DQS0–DQS17 I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data. SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. VDD/VDDQ Supply Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V). VDDSPD Supply SPD EEPROM power supply: +2.3V to +3.6V. VREF Supply SSTL_2 reference voltage (VDD/2). VSS Supply Ground. NC – No connect: These pins are not connected on the module. |
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