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ML610407 Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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ML610407 Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
2 / 36 page FEDL610409-05 ML610407/ML610408/ML610409 2/36 • Capture - Time base capture x 2 channels (4096 Hz to 32 Hz) • PWM - Resolution 16 bits x 1 channel • Synchronous serial port - Master/slave selectable x 2 channels - LSB first/MSB first selectable - 8-bit length/16-bit length selectable • UART - TXD/RXD × 1 channel - Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - Positive logic/negative logic selectable - Built-in baud rate generator • Melody driver - Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) - Tone length: 63 types - Tempo: 15 types - Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter - 16-bit counter - Time division x 2 channels • General-purpose ports - Input-only port: 5 channels (including secondary functions) - Output-only port ML610407: 12 channels (including secondary functions) ML610408: 8 channels (including secondary functions) ML610409: 4 channels (including secondary functions) - Input/output port: 22 channels (including secondary functions) • LCD driver - Number of segments ML610407: Up to 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons) ML610408: Up to 165 dots (select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons) ML610409: Up to 185 dots (select among 37 segments x 5 commons, 38 segments x 4 commons, 39 segments x 3 commons, and 40 segments x 2 commons) - 1/1 to 1/5 duty - 1/2 or 1/3 bias (built-in bias generation circuit) - Frame frequency selectable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) - Bias voltage multiplying clock selectable (8 types) - LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable - Programmable display allocation function • Reset - Reset through the RESET_N pin - Power-on reset generation when powered on - Reset when oscillation stop of the low-speed clock is detected (Cancellation by a mask option is possible) - Reset by the watchdog timer (WDT) overflow |
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