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ML9480 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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ML9480 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 37 page FEDL9480-01 ML9480 9/37 POWER ON/OFF TIMING To turn on the power supply, raise the logic power supply first, then LCD drive power supply in order to prevent the IC from malfunctioning. To fall the power supply, fall the LCD drive power supply first, then the logic power supply. For a VDD pin ranging from 0 V to VDDmin, set VDD ≥ VLCD and t1 ≥ 0 [ns]. To enable the Internal POC circuit, the VDD power supply rise time t2 range needs to be 100 [µs] t2 500 [ms]. For the VDD power supply to turn OFF then turn ON again, it is necessary to secure the POC discharge time t3 100 [ms]. INITIALIZATION SIGNAL TIMING When RESETB signal is externally input The RESETB pin input is valid both for POCEB = "L" and "H". Usable in combination with the POC. Keep the RESETB pin at "L" level until the VDD reaches VDDmin. (t4 ≥ 200[ns]) When Internal POC circuit is used When using the Internal POC circuit in the initialization, set the POCEB pin to "L". At this time, the power ON/OFF timing conditions are t1 to t3 above mentioned. When RESETB pin POC circuit is used If the power ON/OFF timing conditions t1 to t3 cannot be kept, the RESETB pin needs to have a capacitance to configure the POC circuit. For this case, connect a capacitance value according to the power supply rise time. For the power supply rise time t2 and external capacitance value, use the following formula as a guide: CRST [F] > t2 [sec]/(30×10 3) VDD VLCD Time Voltage t1 t1 0.9VDD t2 VDD t3 VDD RESETB VIL t4 VDDmin |
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