HEF4049B datasheet(5/12 Pages) NXP

Part #	HEF4049B

Description	Accepts input voltages in excess of the supply voltage

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HEF4049B

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Product data sheet

Rev. 9 — 18 November 2011

5 of 12

NXP Semiconductors

HEF4049B

Hex inverting buffers

11. Dynamic characteristics

[1]

The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 7.

Dynamic characteristics

VSS = 0 V; CL = 50 pF; tr = tf  20 ns; Tamb = 25 C; unless otherwise specified.

Symbol

Parameter

Conditions

VDD

Extrapolation formula

Min

Typ

Max

Unit

tPHL

HIGH to LOW

propagation delay

nA to nY;

see Figure 5

5 V

[1] 26 ns + (0.18 ns/pF)CL

-35

70

ns

10 V

11 ns + (0.08 ns/pF)CL

-15

30

ns

15 V

9 ns + (0.05 ns/pF)CL

-12

25

ns

tPLH

LOW to HIGH

propagation delay

nA to nY;

see Figure 5

5 V

[1] 23 ns + (0.55 ns/pF)CL

-

50

100

ns

10 V

14 ns + (0.23 ns/pF)CL

-25

50

ns

15 V

12 ns + (0.16 ns/pF)CL

-20

40

ns

tTHL

HIGH to LOW output

transition time

see Figure 5

5 V

[1]

3 ns + (0.35 ns/pF)CL

-20

40

ns

10 V

3 ns + (0.14 ns/pF)CL

-10

20

ns

15 V

2 ns + (0.09 ns/pF)CL

-7

14

ns

tTLH

LOW to HIGH output

transition time

see Figure 5

5 V

[1] 10 ns + (1.00 ns/pF)CL

-

60

120

ns

10 V

9 ns + (0.42 ns/pF)CL

-30

60

ns

15 V

6 ns + (0.28 ns/pF)CL

-20

40

ns

Table 8.

Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.

Symbol

Parameter

VDD

Typical formula for PD (W)

where:

PD

dynamic power

dissipation

5 V

PD = 2500  fi + (fo  CL)  VDD2

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

(f

o  CL) = sum of the outputs.

10 V

PD = 11000  fi + (fo  CL)  VDD2

15 V

PD = 35000  fi + (fo  CL)  VDD2

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