FEDL610Q380FULL-01

ML610Q380/ML610Q383/ML610Q384/ML610Q385

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BLOCK DIAGRAM

Block diagram of ML610Q380

Figure 1-1 is a block diagram of the ML610Q380.

Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.

Program

Memory

（

Flash）

128Kbyte

RAM

2048byte

Interrupt

Controller

CPU (nX-U8/100) Large Model

Timing

Controller

EA

SP

Instruction

Decoder

BUS

Controller

Instruction

Register

TBC

INT

4

INT

6

8bit Timer

× 6

GPIO

NMI

P20 to P23

INT

5

P40 to P43

Data-bus

TEST0

RESET_N

OSC

POWER

RESET &

TEST

ALU

EPSW1-3

PSW

ELR1-3

LR

ECSR1-3

DSR/CSR

PC

GREG

0-15

OUTCLK*

UART

RXD0*

TXD0*

INT

2

LSCLK*

P34 to P35

On-Chip

ICE

P00 to P03

SSIO

SCK0*

SIN0*

SOUT0*

INT

2

WDT

INT

10bit-ADC

AIN0 to AIN3*

3

OSC0*

VOICECNT

SG

INT

1

1

INT

AOUT

INT

1

SDA*

1

SCL*

1

PWM

INT

2

PWM4*

1

PWM5*

1

LCD

Driver

COM0 to COM3

SEG8 to SEG23*

2

LCD

Drive Voltage

XT0

XT1

SPEAKER

AMP

SPP

SPM

SG

SPIN

P44 to P47*

3

P50 to P53

PC0 to PC7*

2

PD0 to PD7*

2

AIN4 to AIN7*

3

BLD

PW45EV0*

1

P30 to P33*

3

TEST1_N

OSC1*

SEG0 to SEG7

P10 to P11

*

*

*

PW45EV1*

1