FEDL610Q346FULL-01

ML610Q346/346

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BLOCK DIAGRAM

Figure 1 is a block diagram of the ML610Q346.

Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding

port.

Figure 1 Block Diagram of ML610Q346

RXD0*

1

TXD0*

1

SCK0*

1

SIN0*

1

SOUT0*

1

Program

Memory

（

Flash）

128Kbyte

RAM

1024byte

Interrupt

Controller

CPU (nX-U8/100)

Timing

Controller

EA

SP

Instruction

Decoder

BUS

Controller

Instruction

Register

TBC

INT

4

INT

2

8bit Timer

×

2

GPIO

NMI

P20 to P23

INT

9

P40 to P47

Data-bus

TEST

RESET_N

OSC

RC32K

POWER

RESET &

TEST

ALU

EPSW1～3

PSW

ELR1～3

LR

ECSR1～3

DSR/CSR

PC

GREG

0～15

OUTCLK*

UART

INT

1

LSCLK*

P30 to P37

On-Chip

ICE

P00 to P07

SSIO

INT

1

WDT

INT

12bit-ADC

AIN0 to AIN2

OSC0

OSC1

VOICECNT

SPP

SPM

SG

INT

1

1

INT

AOUT

OP-AMP0

MOP0_l1

MOP0_l2

MOP0_O

OP-AMP1

MOP1_l1

MOP1_l2

MOP1_O

OP-AMP2

MOP2_l1

MOP2_l2

MOP2_O

SPIN