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MX29GL256FHXGI90Q Datasheet(PDF) 9 Page - Macronix International |
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MX29GL256FHXGI90Q Datasheet(HTML) 9 Page - Macronix International |
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9 / 72 page  9 P/N:PM1544 REV. 1.5, OCT. 30, 2013 MX29GL256F BLOCK DIAGRAM DESCRIPTION The block diagram on Page 8 illustrates a simplified architecture of this device. Each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array. The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC. It creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER" to latch the external address pins A0-AM(A23). The internal addresses are output from this block to the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH AR- RAY". The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" se- lectively through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the flash memo- ry, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls the input and output on the Q0-Q15/A-1 pads. During read operation, the I/O BUFFER receives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program command, the I/O BUFFER transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user in- put pattern. The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module com- prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15/A-1 is latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE REGISTER receives the command and records the current state of the device. The WSM implements the in- ternal algorithms for program or erase according to the current command state by controlling each block in the block diagram. ARRAY ARCHITECTURE The main flash memory array can be organized as Byte mode (x8) or Word mode (x16). The details of the ad- dress ranges and the corresponding sector addresses are shown in Table 1. |
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