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MX29GL128ELXFI90G Datasheet(PDF) 6 Page - Macronix International |
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MX29GL128ELXFI90G Datasheet(HTML) 6 Page - Macronix International |
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6 / 72 page  6 P/N:PM1500 REV. 1.8, NOV. 13, 2013 MX29GL128E BLOCK DIAGRAM DESCRIPTION Theblock diagramillustratesasimplifiedarchitectureofthisdevice.Eachblockintheblockdiagramrepresents oneormorecircuitmodulesintherealchipusedtoaccess,erase,program,andreadthememoryarray. The"CONTROLINPUTLOGIC"blockreceivesinputpinsCE#,OE#,WE#,RESET#,BYTE#,andWP#/ACC. Itcreatesinternaltimingcontrolsignalsaccordingtotheinputpinsandoutputstothe"ADDRESSLATCHAND BUFFER"tolatchtheexternaladdresspinsA0-AM(A22).Theinternaladdressesareoutputfromthisblockto themainarrayanddecoderscomposedof"X-DECODER","Y-DECODER","Y-PASSGATE",AND"FLASHAR- RAY".TheX-DECODERdecodestheword-linesoftheflasharray,whiletheY-DECODERdecodesthebit-lines oftheflasharray.Thebitlinesareelectricallyconnectedtothe"SENSEAMPLIFIER"and"PGMDATAHV"se- lectivelythroughtheY-PASSGATES.SENSEAMPLIFIERSareusedtoreadoutthecontentsoftheflashmemo- ry,whilethe"PGMDATAHV"blockisusedtoselectivelydeliverhighpowertobit-linesduringprogramming.The "I/OBUFFER"controlstheinputandoutputontheQ0-Q15/A-1pads.Duringreadoperation,theI/OBUFFER receivesdatafromSENSEAMPLIFIERSanddrivestheoutputpadsaccordingly.Inthelastcycleofprogram command,theI/OBUFFERtransmitsthedataonQ0-Q15/A-1to"PROGRAMDATALATCH",whichcontrolsthe highpowerdriversin"PGMDATAHV"toselectivelyprogramthebitsinawordorbyteaccordingtotheuserin- putpattern. The"PROGRAM/ERASEHIGHVOLTAGE"blockcomprisesthecircuitstogenerateanddeliverthenecessary highvoltagetotheX-DECODER,FLASHARRAY,and"PGMDATAHV"blocks.Thelogiccontrolmodulecom- prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMANDDATALATCH".WhentheuserissuesacommandbytogglingWE#,thecommandonQ0-Q15/A-1 islatchedintheCOMMANDDATALATCHandisdecodedbytheCOMMANDDATADECODER.TheSTATE REGISTERreceivesthecommandandrecordsthecurrentstateofthedevice.TheWSMimplementsthein- ternalalgorithmsforprogramoreraseaccordingtothecurrentcommandstatebycontrollingeachblockinthe blockdiagram. ARRAY ARCHITECTURE ThemainflashmemoryarraycanbeorganizedasBytemode(x8)orWordmode(x16).Thedetailsofthead- dressrangesandthecorrespondingsectoraddressesareshowninTable 1. |
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