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MX25L6436EZNI10G Datasheet(PDF) 3 Page - Macronix International |
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MX25L6436EZNI10G Datasheet(HTML) 3 Page - Macronix International |
3 / 68 page 3 MX25L6436E P/N: PM1772 REV. 2.0, AUG. 02, 2012 BP and SRWD if WPSEL=0 ............................................................................................................................. 29 The individual block lock mode is effective after setting WPSEL=1................................................................. 30 WPSEL Flow .................................................................................................................................................... 31 (25) Single Block Lock/Unlock Protection (SBLK/SBULK)............................................................................... 32 Block Lock Flow ............................................................................................................................................... 32 Block Unlock Flow............................................................................................................................................ 33 (26) Read Block Lock Status (RDBLOCK)....................................................................................................... 34 (27) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 34 (28) Clear SR Fail Flags (CLSR)...................................................................................................................... 34 (29) Enable SO to Output RY/BY# (ESRY)...................................................................................................... 34 (30) Disable SO to Output RY/BY# (DSRY)..................................................................................................... 34 (31) Read SFDP Mode (RDSFDP)................................................................................................................... 35 Table 7. Signature and Parameter Identification Data Values .................................................................. 36 Table 8. Parameter Table (0): JEDEC Flash Parameter Tables ................................................................ 37 Table 9. Parameter Table (1): Macronix Flash Parameter Tables ............................................................. 39 POWER-ON STATE ...................................................................................................................................................41 ELECTRICAL SPECIFICATIONS..............................................................................................................................42 ABSOLUTE MAXIMUM RATINGS................................................................................................................... 42 Figure 3. Maximum Negative Overshoot Waveform .................................................................................42 CAPACITANCE TA = 25°C, f = 1.0 MHz........................................................................................................... 42 Figure 4. Maximum Positive Overshoot Waveform...................................................................................42 Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL.....................................................43 Figure 6. OUTPUT LOADING ..................................................................................................................43 Table 10. DC CHARACTERISTICS ......................................................................................................... 44 Table 11. AC CHARACTERISTICS .......................................................................................................... 45 Timing Analysis ........................................................................................................................................................47 Figure 7. Serial Input Timing .....................................................................................................................47 Figure 8. Output Timing.............................................................................................................................47 Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1..........................................48 Figure 10. Write Enable (WREN) Sequence (Command 06)....................................................................48 Figure 11. Write Disable (WRDI) Sequence (Command 04).....................................................................48 Figure 12. Read Identification (RDID) Sequence (Command 9F).............................................................49 Figure 13. Read Status Register (RDSR) Sequence (Command 05).......................................................49 Figure 14. Write Status Register (WRSR) Sequence (Command 01) ......................................................49 Figure 15. Read Data Bytes (READ) Sequence (Command 03) ..............................................................50 Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ..........................................50 Figure 17. Dual Read Mode Sequence (Command 3B) ...........................................................................50 Figure 18. Quad Read Mode Sequence (Command 6B)..........................................................................51 Figure 19. Sector Erase (SE) Sequence (Command 20)..........................................................................52 Figure 20. Block Erase (BE/BE32K) Sequence (Command D8/52)..........................................................52 Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)...................................................................52 Figure 22. Page Program (PP) Sequence (Command 02) .......................................................................53 Figure 23. 4 x I/O Page Program (4PP) Sequence (Command 38)..........................................................53 Figure 24. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)..........54 Figure 25. Deep Power-down (DP) Sequence (Command B9) ................................................................54 Figure 26. Read Electronic Signature (RES) Sequence (Command AB)..................................................55 Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) .......................................55 Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)..56 |
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