Detailed Description

The MAX6412–MAX6420 low-power microprocessor

(µP) supervisory circuits provide maximum adjustability

for supply-voltage monitoring and reset functionality. In

addition, the MAX6412–MAX6420 reset timeout period

is adjustable using an external capacitor.

The MAX6412/MAX6413/MAX6414 have factory-

trimmed reset threshold voltages in approximately

100mV increments from 1.575V to 5.0V with a manual

reset input. The MAX6415/MAX6416/MAX6417 contain

a reset threshold that can be adjusted to any voltage

above 1.26V using external resistors. The MAX6418/

MAX6419/MAX6420 offer both a factory-trimmed reset

threshold and an adjustable reset threshold input for

dual-voltage monitoring.

falls below the preset values or when MR is asserted.

The reset remains asserted for an externally pro-

above the reset threshold or MR is deasserted.

Reset Output

The reset output is typically connected to the reset

input of a µP. A µP’s reset input starts or restarts the µP

in a known state. The MAX6412–MAX6420 µP supervi-

sory circuits provide the reset logic to prevent code-

execution errors during power-up, power-down, and

brownout conditions (see

Typical Operating Circuit).

For the MAX6413, MAX6416, and MAX6419, RESET

drops below the reset threshold voltages. Once RESET

age(s), RESET remains high for the reset timeout period,

then goes low.

teed to be a logic high. For applications requiring valid

The active-low RESET output of the remaining supervi-

sors is the inverse of the MAX6413, MAX6416, and

MAX6419 active-high RESET output and is guaranteed

Reset Threshold

The MAX6415–MAX6420 monitor the voltage on RESET

IN with an external resistor voltage-divider (Figure 1).

Low-Power, Single/Dual-Voltage µP Reset Circuits

with Capacitor-Adjustable Reset Timeout Delay

MAX6412–MAX6420

Maxim Integrated

5

Pin Description

PIN

MAX6412/

MAX6413/

MAX6414

MAX6415/

MAX6416/

MAX6417

MAX6418/

MAX6419/

MAX6420

NAME

FUNCTION

RESET

manual reset is pulled low. RESET remains low for the reset timeout period

after all reset conditions are deasserted and then goes high.

11

1

RESET

reset is pulled low. RESET remains high for the reset timeout period after all

reset conditions are deasserted and then goes low.

2

2

2

GND

Ground

—3

3

RESET

IN

Reset Input. High-impedance input to the adjustable reset comparator.

Connect RESET IN to the center point of an external resistor-divider

network to set the threshold of the externally monitored voltage. See Reset

Threshold section.

3—

—

MR

Manual Reset Input. Pull this pin low to manually reset the device. Reset

remains asserted for the reset timeout period after MR is released.

444

SRT

Set Reset Timeout Input. Connect a capacitor between SRT and ground to

set the timeout period. Determine the period as follows:

555