MX25L6435EZNI10G datasheet(6/89 Pages) MCNIX

Part #	MX25L6435EZNI10G

Description	64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

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MX25L6435E

P/N: PM1784

REV. 1.4, NOV. 05, 2013

2. GENERAL DESCRIPTION

MX25L6435E is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two

or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25L6435E feature a se-

rial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O

mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Se-

rial access to the device is enabled by CS# input.

MX25L6435E, MXSMIO® (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and

multi-I/O features.

When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input

and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin,

SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for Continuous Program mode, and erase command is executed on sector (4K-byte),

block (32K-byte/64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status

read command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25L6435E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read Performance

Numbers of Dummy Cycles

4 I/O

6

86*

8

104

Note: *means default status

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