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MX25L3273EMI10G Datasheet(PDF) 9 Page - Macronix International

Part # MX25L3273EMI10G
Description  32M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY
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Manufacturer  MCNIX [Macronix International]
Direct Link  http://www.macronix.com
Logo MCNIX - Macronix International

MX25L3273EMI10G Datasheet(HTML) 9 Page - Macronix International

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MX25L3273E
P/N: PM1906
REV. 1.1, NOV. 07, 2013
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and complet-
ed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuous Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic
Signature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be pro-
tected as read only. The protected area definition is shown as table of "Table 2. Protected Area Sizes", the
protected areas are more flexible which may protect various areas by setting value of BP0-BP3 bits.
- MX25L3273E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.


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