10

MX25L5121E

MX25L1021E

P/N: PM1573

REV. 1.3, NOV. 11, 2013

DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

• Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.

• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data

change.

• Deep Power Down Mode: By entering Deep Power Down Mode, the flash device also is under protected from

writing all commands except Release from Deep Power Down Mode command (RDP).

Table 2. Protected Area Sizes

Status bit

Protect level

BP1

BP0

MX25L5121E

MX25L1021E

0

0

0 (none)

0 (none)

0

1

1 (All)

1 (1 block)

1

0

2 (All)

2 (All)

1

1

3 (All)

3 (All)