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90-0107 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. 90-0107
Description  I2C Serial Real-Time Clock
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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DS1339 I
2C Serial Real-Time Clock
5 of 20
POWER-UP/DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 2, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
tREC
(Note 16)
2
ms
VCC Fall Time; VPF(MAX) to VPF(MIN)
tVCCF
300
µs
VCC Rise Time; VPF(MIN) to VPF(MAX)
tVCCR
0
µs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Note 2:
Limits at -40°C are guaranteed by design and are not production tested.
Note 3:
SCL only.
Note 4:
SDA and SQW/
INT.
Note 5:
ICCA—SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charger disabled.
Note 6:
Specified with the I
2C bus inactive, V
IL = 0.0V, VIH = VCC, trickle charger disabled.
Note 7:
VCC must be less than 3.63V if the 250Ω resistor is selected.
Note 8:
Using recommended crystal on X1 and X2.
Note 9:
Guaranteed by design; not production tested.
Note 10:
After this period, the first clock pulse is generated.
Note 11:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
Note 12:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line
is released.
Note 14:
CB—total capacitance of one bus line in pF.
Note 15:
The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤
VCC ≤ VCCMAX and 1.3V ≤ VBACKUP ≤ 3.7V.
Note 16:
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
Figure 1. Power-Up/Down Timing
OUTPUTS
VCC
V
PF(MAX)
V
PF(MIN)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZED
RECOGNIZED
VALID
t
VCCF
t
VCCR
t
REC




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