CYD18S18V18-200BBAXC datasheet(8/53 Pages) CYPRESS

Part #	CYD18S18V18-200BBAXC

Description	FullFlex Synchronous SDR Dual Port SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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8 / 53 page

Document Number: 38-06082 Rev. *O

Page 8 of 53

CYDXXS72V18

CYDXXS36V18

CYDXXS18V18

Figure 5. FullFlex18 SDR 256-ball BGA (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

DNU

DQ17L

DQ16L

DQ13L

DQ12L

DQ9L

DQ9R

DQ12R

DQ13R

DQ16R

DQ17R

DNU

B

DNU

DQ15L

DQ14L

DQ11L

DQ10L

DQ10R

DQ11R

DQ14R

DQ15R

DNU

C

DNU

RETL

INTL

CQ1L

DNU

TRST

MRST

ZQ0R[17]

CQ1R

INTR

RETR

DNU

D

A0L

A1L

WRPL

VREFL

FTSELL

LOWSPDL

VSS

VTTL

VSS

LOWSPDR

FTSELR

VREFR

WRPR

A1R

A0R

E

A2L

A3L

CE0L

CE1L

VDDIOL

VCORE

VDDIOR

CE1R

CE0R

A3R

A2R

F

A4L

A5L

CNTINTL

DNU

VDDIOL

VSS

VDDIOR

DNU

CNTINTR

A5R

A4R

G

A6L

A7L

BUSYL

DNU

ZQ0L[17]

VSS

VDDIOR

DNU

BUSYR

A7R

A6R

H

A8L

A9L

CL

VTTL

VCORE

VSS

VCORE

VTTL

CR

A9R

A8R

J

A10L

A11L

VSS

PORTSTD1L

VCORE

VSS

VCORE

PORTSTD1R

VSS

A11R

A10R

K

A12L

A13L

OEL

BE1L

VDDIOL

VSS

VDDIOR

BE1R

OER

A13R

A12R

L

A14L

A15L

ADSL

BE0L

VDDIOL

VSS

VDDIOR

BE0R

ADSR

A15R

A14R

M

A16L

A17L

R/WL

CQENL

VDDIOL

VCORE

VDDIOR

CQENR

R/WR

A17R

A16R

N

A18L[19]

A19L[18]

CNT/MSKL

VREFL

PORTSTD0L

READYL

DNU

VTTL

DNU

READYR

PORTSTD0R

VREFR

CNT/MSKR

A19R[18]

A18R[19]

P

DNU

CNTENL

CNTRSTL

CQ0L

TCK

TMS

TDO

TDI

CQ0R

CNTRSTR

CNTENR

DNU

R

DNU

DQ6L

DQ5L

DQ2L

DQ1L

DQ1R

DQ2R

DQ5R

DQ6R

DNU

T

DNU

DQ8L

DQ7L

DQ4L

DQ3L

DQ0L

DQ0R

DQ3R

DQ4R

DQ7R

DQ8R

DNU

Notes

17. Leave this ball unconnected to disable VIM.

18. Leave this ball unconnected for CYD09S18V18.

19. Leave this ball unconnected for CYD04S18V18.

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