Datasheet

Datasheet

11/15

TSZ02201-0P1P0B000610-1-2

© 2014 ROHM Co., Ltd. All rights reserved.

14.JAN.2014 Rev.001

www.rohm.com

TSZ22111 • 15 • 001

BD63005MUV

I/O Equivalence Circuits

FGSW

PWMB

BRKB

CW

100k

Ω

10k

Ω

VREG

ENB

100k

Ω

10k

Ω

Internal

Reg

VCC

VREG

145k

Ω

50k

Ω

HUP

HUN

HVP

HVN

HWP

HWN

VREG

2k

Ω

RCL

250k

Ω

2k

Ω

VREG

VCC

U

V

W

RNF

FGO

5

Ω

CLNMT

LPE

100k

Ω

10k

Ω

VREG

10k

Ω

Internal

Reg

CP1

20

Ω

CP2

20

Ω

VG

VCC

Power Dissipation

VQFN040V6060 package has metal for heat dissipation on backside of IC. It is supposed to use this metal for processing

heat dissipation, so please connect to GND plane on board by soldering and keep GND pattern as large as possible to get

enough heat dissipation area. It is impossible to keep power dissipation as shown below without soldering. The Backside

metal is shorted to backside of IC chip and it is also GND potential. Therefore please do not make wiring pattern other than

GND right under backside metal of IC, since malfunction and destruction of IC might occur by being shorted to potential other

than GND.

Package thermal resistor

Board

Board ①

125

Board ②

33.2

Board ③

26.8

PCB size：74.2mm×74.2mm×1.6mm

Board①：1 layer PCB (1 layer：23.69mm

Board②：4 layer PCB (1,4 layer：23.69mm

Board③：4 layer PCB (all layers：5505mm

()：Copper foil pattern area size

Caution：Values about heat reducing curve and packaged thermal

resistor are tested values.

Figure 6. I/O Equivalence Circuits

0. 0

1. 0

2. 0

3. 0

4. 0

5. 0

0

25

50

75

100

125

150

AMBIENT TEMPERATURE [°C]

③4.66W

①1.00W

②3.77W

Figure 7. Derating Curve

(VQFN040V6060)