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CYD18S72V18 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CYD18S72V18
Description  FullFlex Synchronous SDR Dual Port SRAM
Download  53 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYD18S72V18 Datasheet(HTML) 6 Page - Cypress Semiconductor

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Document Number: 38-06082 Rev. *O
Page 6 of 53
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 3. FullFlex18 SDR 484-ball BGA Pinout (Top View)[11]
1
2
3
45678
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A DNU DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ15L
DQ12L
DQ9L
DQ9R
DQ12R
DQ15R
DNU
DNU
DNU
DNU
DNU
DNU
DNU DNU
B DNU DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ16L
DQ13L
DQ10L
DQ10R
DQ13R
DQ16R
DNU
DNU
DNU
DNU
DNU
DNU
DNU DNU
C DNU DNU
VSS
VSS
DNU
DNU
DNU
DNU
DQ17L
DQ14L
DQ11L
DQ11R
DQ14R
DQ17R
DNU
DNU
DNU
DNU
VSS
VSS
DNU DNU
D DNU DNU
VSS
VSS
VSS
CQ1L
CQ1L
VSS
LOWSPDL
PORTSTD0L
ZQ0L[12] BUSYL CNTINTL PORTSTD1L
DNU
CQ1R
CQ1R
VSS
VSS
VSS
DNU DNU
E DNU DNU VDDIOL
VSS
VSS
VDDIOL VDDIOR VDDIOR VDDIOR
VDDIOR
VTTL
VTTL
VTTL
VDDIOL
VDDIOL VDDIOL VDDIOL
DNU
VSS
VDDIOR DNU DNU
F
DNU DNU
CE1L
CE0L
VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR
VCORE
VCORE VCORE
VCORE
VDDIOL
VDDIOL VDDIOL VDDIOR VDDIOR
CE0R
CE1R
DNU DNU
G
A0L
A1L
RETL
BE1L
VDDIOL VDDIOL VREFL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREFR VDDIOR VDDIOR
BE1R
RETR
A1R A0R
H
A2L
A3L
WRPL
DNU
VDDIOL VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR VDDIOR
DNU
WRPR
A3R A2R
J
A4L
A5L
READYL
DNU
VDDIOL VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR VDDIOR
DNU
READYR A5R A4R
K
A6L
A7L
ZQ1L[12]
DNU
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCORE VDDIOR
DNU
ZQ1R[12]
A7R A6R
L
A8L
A9L
CL
OEL
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
OER
CR
A9R A8R
M A10L A11L
VSS
DNU
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
DNU
VSS
A11R A10R
N A12L A13L
ADSL
DNU
VDDIOL VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
DNU
ADSR
A13R A12R
P A14L A15L CNT/MSKL
DNU
VDDIOL VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR VDDIOR
DNU
CNT/MSKR
A15R A14R
R A16L A17L CNTENL
BE0L
VDDIOL VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR VDDIOR
BE0R
CNTENR A17R A16R
T A18L A19L CNTRSTL
INTL
VDDIOL VDDIOL VREFL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREFR VDDIOR VDDIOR
INTR
CNTRSTR
A19R A18R
U A20L DNU
R/WL
CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR
VCORE
VCORE VCORE
VCORE
VDDIOL
VDDIOL VDDIOL VDDIOR VDDIOR CQENR
R/WR
DNU A20R
V DNU DNU FTSELL VDDIOL
DNU
VDDIOR VDDIOR VDDIOR VDDIOR
VTTL
VTTL
VTTL
VDDIOL
VDDIOL
VDDIOL VDDIOL VDDIOR
TRST
VDDIOR FTSELR
DNU DNU
W DNU DNU
VSS
MRST
VSS
CQ0L
CQ0L
DNU
PORTSTD1R
CNTINTR BUSYR ZQ0R[12] PORTSTD0R LOWSPDR
VSS
CQ0R
CQ0R
VSS
TDI
TDO
DNU DNU
Y DNU DNU
VSS
VSS
DNU
DNU
DNU
DNU
DQ8L
DQ5L
DQ2L
DQ2R
DQ5R
DQ8R
DNU
DNU
DNU
DNU
TMS
TCK
DNU DNU
AA DNU DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ7L
DQ4L
DQ1L
DQ1R
DQ4R
DQ7R
DNU
DNU
DNU
DNU
DNU
DNU
DNU DNU
AB DNU DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ6L
DQ3L
DQ0L
DQ0R
DQ3R
DQ6R
DNU
DNU
DNU
DNU
DNU
DNU
DNU DNU
Notes
11. Use this pinout only for device CYD36S18V18 of the FullFlex18 family.
12. Leave this ball unconnected to disable VIM.


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