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CY7C346B-25JCJI Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C346B-25JCJI Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 15 page  USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C346B Document #: 38-03037 Rev. *C Page 7 of 15 Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range Parameter Description 7C346B-25 7C346B-35 Unit Min. Max. Min. Max. tPD1 Dedicated Input to Combinatorial Output Delay[4] 25 35 ns tPD2 I/O Input to Combinatorial Output Delay[4] 40 55 ns tSU Global Clock Set-Up Time 15 25 ns tCO1 Synchronous Clock Input to Output Delay[4] 14 20 ns tH Input Hold Time from Synchronous Clock Input 0 0 ns tWH Synchronous Clock Input HIGH Time 8 12.5 ns tWL Synchronous Clock Input LOW Time 8 12.5 ns fMAX Maximum Register Toggle Frequency[5] 62.5 40 MHz tCNT Minimum Global Clock Period 20 30 ns tODH Output Data Hold Time After Clock 2 2 ns fCNT Maximum Internal Global Clock Frequency[6] 50 33.3 MHz Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range Parameter Description 7C346B-25 7C346B-35 Unit Min. Max. Min. Max. tACO1 Asynchronous Clock Input to Output Delay[4] 25 35 ns tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input 510 ns tAH Input Hold Time from Asynchronous Clock Input 6 10 ns tAWH Asynchronous Clock Input HIGH Time[7] 11 16 ns tAWL Asynchronous Clock Input LOW Time[7] 914 ns tACNT Minimum Internal Array Clock Frequency 20 30 ns fACNT Maximum Internal Array Clock Frequency[6] 50 33.3 MHz Commercial and Industrial Internal Switching Characteristics Over Operating Range Parameter Description 7C346B-25 7C346B-35 Unit Min. Max. Min. Max. tIN Dedicated Input Pad and Buffer Delay 5 11 ns tIO I/O Input Pad and Buffer Delay 6 11 ns tEXP Expander Array Delay 12 20 ns tLAD Logic Array Data Delay 12 14 ns tLAC Logic Array Control Delay 10 13 ns tOD Output Buffer and Pad Delay[4] 56 ns tZX Output Buffer Enable Delay[4] 10 13 ns tXZ Output Buffer Disable Delay[8] 10 13 ns tRSU Register Set-Up Time Relative to Clock Signal at Register 612 ns tRH Register Hold Time Relative to Clock Signal at Register 48 ns tLATCH Flow Through Latch Delay 3 4 ns tRD Register Delay 1 2 ns Notes: 4. C1 = 35 pF. 5. The fMAX values represent the highest frequency for pipeline data. 6. This parameter is measured with a 16-bit counter programmed into each LAB. 7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped. 8. C1 = 5 pF. |
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