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CAT64LC40JTE13 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT64LC40JTE13 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 9 page Discontinued Parts 5 CAT64LC10/20/40 Doc. No. 1021, Rev. C INSTRUCTION SET Instruction Opcode Address Data Read 64LC10 10101000 A5 A4 A3 A2 A1 A0 0 0 D15 - D0 64LC20 10101000 A6 A5 A4 A3 A2 A1 A0 0 D15 - D0 64LC40 10101000 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 Write 64LC10 10100100 A5 A4 A3 A2 A1 A0 0 0 D15 - D0 64LC20 10100100 A6 A5 A4 A3 A2 A1 A0 0 D15 - D0 64LC40 10100100 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 Write Enable 10100011 X X X X X X X X Write Disable 10100000 X X X X X X X X [Write All Locations](1) 10100001 X X X X X X X X D15–D0 Figure 1. A.C. Testing Input/Output Waveform (2)(3(4) (CL = 100 pF) Note: (1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications. (2) Input Rise and Fall Times (10% to 90%) < 10 ns. (3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8. (4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7. INPUT PULSE LEVELS REFERENCE POINTS VCC x 0.7 VCC x 0.3 VCC x 0.8 VCC x 0.2 |
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