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CAT93C6631 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
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CAT93C6631 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
3 / 10 page 9-87 CAT93CXXXX Stock No. 21084-01 2/98 Advanced Information A.C. CHARACTERISTICS VCC=2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF Power-Up Timing(1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Limits VCC =VCC = 2.7V -6V 4.5V-5.5V Test SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions tCSS CS Setup Time 250 50 ns tCSH CS Hold Time 0 0 ns tDIS DI Setup Time 250 50 ns tDIH DI Hold Time 250 50 ns tPD1 Output Delay to 1 0.5 0.1 µs tPD0 Output Delay to 0 0.5 0.1 µs tHZ(1) Output Delay to High-Z 500 100 ns tEW Program/Erase Pulse Width 5 5 ms tCSMIN Minimum CS Low Time 0.5 0.1 µs tSKHI Minimum SK High Time 0.5 0.1 µs tSKLOW Minimum SK Low Time 0.5 0.1 µs tSV Output Delay to Status Valid 0.5 0.1 µs SKMAX Maximum Clock Frequency DC 1000 DC 3000 KHZ CL = 100pF CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(1) Input/Output Capacitance 8 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method NEND(1) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(1)(3) Latch-up 100 mA JEDEC Standard 17 |
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