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CAT34WC02JA-1.8TE13 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT34WC02JA-1.8TE13 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
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5 / 10 page  CAT34WC02 5 Doc No. 1003, Rev. A I2C BUS PROTOCOL The following defines the features of the I2C bus proto- col: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT34WC02 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed (except when accessing the Write Protect Register) as 1010 for the CAT34WC02 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to eight CAT34WC02 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT34WC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT34WC02 then performs a Read or a Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg- ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT34WC02 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. When the CAT34WC02 begins a READ mode, it trans- mits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this ac- knowledge, the CAT34WC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. 34WC02 F07 Figure 4. Acknowledge Timing Figure 5. Slave Address Bits 5020 FHD F06 ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 1 DEVICE ADDRESS 0 1 0 A2 A1 A0 R/W 0 1 1 0 A2 A1 A0 R/W Normal Read and Write Programming the Write Protect Register |
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