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CAT28F512P-90T Datasheet(PDF) 11 Page - Catalyst Semiconductor |
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CAT28F512P-90T Datasheet(HTML) 11 Page - Catalyst Semiconductor |
11 / 14 page CAT28F512 11 Preliminary Doc. No. 25042-00 2/98 F-1 ADDRESSES CE (E) OE (G) WE (W) DATA (I/O) VCC VPP tWC tWC tRC tAS tAH tCS tCH tCS tCH tCH tEHQZ tDF tGHWL tWPH tWHWH1 tWHGL tWP tDS HIGH-Z DATA IN = 40H DATA IN DATA IN = C0H VALID DATA OUT tDH tWP tDH tDS tDS tWP tDH tOLZ tOE tOH tLZ tCE tVPEL VPPH VPPL 0V 5.0V VCC POWER-UP & STANDBY SETUP PROGRAM COMMAND LATCH ADDRESS & DATA PROGRAMMING PROGRAM VERIFY COMMAND PROGRAM VERIFICATION VCC POWER-DOWN/ STANDBY Erase-Verify Mode The Erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. Programming Mode The programming operation is initiated using the pro- gramming algorithm of Figure 7. During the first write cycle, the command 40H is written into the command register. During the second write cycle, the address of the memory location to be programmed is latched on the falling edge of WE, while the data is latched on the rising edge of WE. The program operation terminates with the next rising edge of WE. An integrated stop timer allows for automatic timing control over this operation, eliminat- ing the need for a maximum program timing specifica- tion. Refer to AC Characteristics (Program/Erase) for specific timing parameters. 28F512 F08 Figure 6. A.C. Timing for Programming Operation Program-Verify Mode A Program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Program- verify operation is initiated by writing C0H into the command register. An internal reference generates the necessary high voltages so that the user does not need to modify VCC. Refer to AC Characteristics (Program/ Erase) for specific timing parameters. |
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