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CAT35C704 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
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CAT35C704 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
3 / 14 page Preliminary CAT35C704 3 Doc. No. 25045-00 2/98 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tHZ is measured from the falling edge of the clock to the time when the output is no longer driven. A.C. CHARACTERISTICS VCC = +5V ±10%,unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions tCSS CS Setup Time 150 ns tCSH CS Hold Time 0 ns CL = 100pF tDIS DI Setup Time 50 ns VIN = VIH or VIL tDIH DI Hold Time 0 ns VOUT = VOH or VOL tPD CLK to DO Delay 150 ns tHZ(1) (2) CLK to DO High-Z Delay 50 ns tEW Program/Erase Pulse Width 12 ms tCSL CS Low Pulse Width 200 ns tCKH CLK High Pulse Width 165 ns tCKL CLK Low Pulse Width 100 ns tSV ERR Output Delay 150 ns CL = 100pF tVCCS(1) VCC to CS Setup Time 5 µsCL = 100pF tCSZ(1) CS to DO High-Z Delay 50 ns tCSD CS to DO Busy Delay 150 ns fCLK Clock Frequency DC 3 MHz |
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