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CAT25C17S-1.8TE13 Datasheet(PDF) 1 Page - Catalyst Semiconductor |
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CAT25C17S-1.8TE13 Datasheet(HTML) 1 Page - Catalyst Semiconductor |
1 / 10 page 1 CAT25C03/05/09/17/33 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES s 10 MHz SPI Compatible s 1.8 to 6.0 Volt Operation s Hardware and Software Protection s Zero Standby Current s Low Power CMOS Technology s SPI Modes (0,0 &1,1) s Commercial, Industrial and Automotive Temperature Ranges s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Self-Timed Write Cycle s 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP s Page Write Buffer s Write Protection – Protect First Page, Last Page, Any 1/4 Array or Lower 1/2 Array PIN CONFIGURATION DIP Package (P) SOIC Package (S16) PIN FUNCTIONS Pin Name Function SO Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input NC No Connect BLOCK DIAGRAM © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Advanced DESCRIPTION The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM internally organized as 256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst’s advanced CMOS Technology substantially reduces de- vice power requirements. The CAT25C03/05 features a 16-byte page write buffer. The 25C09/17/33 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select ( CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C03/05/09/17/33 is de- signed with software and hardware write protection features. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP packages. TSSOP Package (U14) SENSE AMPS SHIFT REGISTERS SPI CONTROL LOGIC WORD ADDRESS BUFFERS I/O CONTROL E2PROM ARRAY COLUMN DECODERS XDEC HIGH VOLTAGE/ TIMING CONTROL SO 25C128 F02 STATUS REGISTER BLOCK PROTECT LOGIC DATA IN STORAGE SI CS WP HOLD SCK SOIC Package (S) VSS SO WP VCC HOLD SCK SI 1 2 3 4 8 7 6 5 CS SO WP CS VCC SCK SI 1 2 3 4 8 7 6 5 VSS HOLD CS NC 1 2 3 4 14 13 12 11 NC NC NC 5 6 710 9 8 NC SCK VSS SI NC WP VCC HOLD SO 15 16 NC NC CS WP HOLD VCC NC NC NC NC SO NC NC VSS SCK SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSSOP Package (U) 8 7 6 5 VCC WP SCL CS VSS 1 2 3 4 SO HOLD SI Doc. No. 25068-00 2/98 |
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