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CAT25CXXX Datasheet(PDF) 5 Page - Catalyst Semiconductor

Part No. CAT25CXXX
Description  Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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 5 page
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9-99
CAT25CXXX
Stock No. 21085-01 4/98
Advanced
FUNCTIONAL DESCRIPTION
The CAT25CXXX supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25CXXX to interface directly
with many of today’s popular microcontrollers. The
CAT25CXXX contains an 8-bit instruction register. (The
instruction set and the operation codes are detailed in
the instruction set table)
After the device is selected with
CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
WP
WP
WP
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP going low will
have no effect on any write operation to the status
register. The
WP pin function is blocked when the WPEN
bit is set to 0.
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 X011(1)
Read Data from Memory
WRITE
0000 X010(1)
Write Data to Memory
INSTRUCTION SET
RESET/
RESET
RESET
RESET
RESET
RESET: RESET I/O
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins the
device will initiate and maintain a reset condition. RE-
SET pin must be connected through a pull-down and
RESET pin must be connected through a pull-up device.
CS
CS
CS
CS
CS: Chip Select
CS is the Chip select pin. CSlow enables the CAT25CXXX
and
CS high disables the CAT25CXXX. CS high takes
the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway) The CAT25CXXX draws ZERO
current in the Standby mode. A high to low transition on
CS is required prior to any sequence being initiated. A
low to high transition on
CS after a valid write sequence
is what initiates an internal write cycle.
Note:
(1) X=O for 25C02X/08X/16X/32X. X=A8 for 25C04X
76543210
WPEN
X
WD1
WD0
BP1
BP0
WEL
RDY
STATUS REGISTER
opcodes, byte addresses, and data to be written to the
25CXXX. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25CXXX. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25CXXX. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.




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