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IRS2166DSPBF Datasheet(PDF) 10 Page - International Rectifier |
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IRS2166DSPBF Datasheet(HTML) 10 Page - International Rectifier |
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10 / 18 page  IRS2166D(S)PbF www.irf.com Page 10 4 3 5uA 5 2 CPH C T RPH R T 11 12 COM LO M2 RCS OSC. 16 HO M1 15 VS R T C CPH C T Half- Bridge Output I LOAD V BUS(+) V BUS (-) Load Return Half- Bridge Driver IRS2166D S4 R PH Fig. 3: Preheat circuitry gate of a p-channel MOSFET (S4) (see Fig. 4) that connects pin RPH with pin RT. As pin CPH exceeds 10.8 V (VCPHEOP), the gate-to-source voltage of MOSFET S4 begins to fall below the turn-on threshold of S4. As pin CPH continues to ramp towards V CC, switch S4 turns off slowly. This results in resistor RPH being disconnected smoothly from resistor RT, which causes the operating frequency to ramp smoothly from the preheat frequency, through the ignition frequency, to the final run frequency. The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half-bridge MOSFET current flowing through the external current sensing resistor RCS. The resistor RCS therefore programs the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs. Should this voltage exceed the internal threshold of 1.20 V (VCSTH+), the internal fault counter begins counting the number of of sequential over-current faults (see timing diagram). If the number of over-current faults exceeds 50 (nEVENTS), the IC will enter FAULT mode and gate driver outputs HO, LO and PFC will be latched low. Run Mode (RUN) Once the lamp has successfully ignited, the ballast enters run mode. The run mode is defined as the state the IC is in when the lamp arc is established and the lamp is being driven to a given power level. The run mode oscillating frequency is determined by the timing resistor RT and timing capacitor CT (see Design Equations, page 15). Should hard-switching occur at the half-bridge at any time due to an open-filament or lamp removal, the voltage across the current sensing resistor, RCS, will exceed the internal threshold of 1.20 V (VCSTH+) and the fault counter will begin counting (see timing diagram). Should the number of consecutive over-current faults exceed 50 (nEVENTS), the IC will enter fault mode and gate driver outputs HO, LO and PFC will be latched low. Fig.4: Ignition circuitry DC Bus Undervoltage Reset Should the DC bus decrease too low during a brown-out line condition or over-load condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard-switching at the half-bridge which can damage the half-bridge switches or, the DC bus can decrease too far and the lamp can extinguish. To protect against this, the VBUS pin includes a 3.0 V undervoltage threshold (VBUSUV). Should the voltage at the VBUS pin decrease below 3.0 V, VCC will be discharged below the VCCUV- threshold and all gate driver outputs will be latched low. For proper ballast design, the designer should design the PFC section such that the DC bus does not drop until the AC line input voltage falls below the rated input voltage of the ballast (see PFC section). When correctly designed, the voltage measured at the VBUS pin will decrease below the internal 3.0 V threshold (VBUSUV) and the ballast will turn off cleanly. The pull-up resistor to VCC (RSUPPLY) will then turn the ballast on again when the AC input line voltage increases to the minimum specified value causing VCC to exceed VCCUV+. RSUPPLY should be set to turn the ballast on at the minimum specified ballast input voltage. The PFC should then be designed such that the DC bus decreases at an input line voltage that is lower than the minimum specified ballast input voltage. This hysteresis will result in clean turn-on and turn-off of the ballast. SD/EOL and CS Fault Mode (FAULT) Should the voltage at the SD/EOL pin exceed 3.0 V (VEOLTH+) or decrease below 1.0 V (VEOLTH-) during run mode, an end-of-life (EOL) fault condition has occurred and the IC enters fault mode. LO, HO, and PFC gate driver outputs are all latched off in the ‘low’ state. CPH is discharged to COM for resetting the preheat time. To exit fault mode, VCC can be decreased below VCCUV- (ballast power off) or the SD pin can be increased above 5.0 V (VSDTH+) (lamp removal). Either of these will force the IC to enter UVLO mode (see State Diagram, page 7). Once 4 3 5uA 5 2 CPH CT RPH RT 11 12 COM LO M2 R CS OSC 16 HO M1 15 VS C CPH C T Half- Bridge Output I LOAD (+) V BUS (-) Load Return Half- Bridge Driver IRS2166D 1.3V S 1 S 4 Comp 4 10 13 VCC CS R1 C CS S 3 Fault Logic V BUS R T R PH |
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