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IRMCF171 Datasheet(PDF) 7 Page - International Rectifier |
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IRMCF171 Datasheet(HTML) 7 Page - International Rectifier |
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7 / 36 page  IRMCF171 7 www.irf.com © 2013 International Rectifier April 20, 2013 3 IRMCF171 Block Diagram and Main Functions IRMCF171 block diagram for leg shunt mode is shown in Figure 3. Motion Control Sequencer Dual Port RAM 2 KB MCE Program RAM 12 KB Program FLASH 64 KB A/D MUX S/H D/A (PWM) Timer Counnter 0,1,2 Watchdog Timer Motion Control Modules UART I2C SND RCV 6 Low Loss SVPWM AIN0 GATEKILL To IGBT gate drive Flexible Motion Control Engine (MCE) Monitoring Host Interface Digital I/Os 8bit (8051) microcontroller AIN1 AIN2 JTAG Emulator Debugger 4 Freq Synthesizer 2 Ceramic Resonator (4MHz) 20MHz AIN3 analog input 2 Capture Interrupt Control Single Shunt Motor Current Reconstruction From shunt resistor Speed command PORT 1 SCL SDA PORT 2 PORT 3 AIN4 8bit CPU Core Local RAM 2 KB 120MHz IFB 3 AIN5 3 Figure 3. IRMCF171 Block Diagram IRMCF171 contains the following functions for sensorless AC motor control applications: Motion Control Engine (MCETM) Sensorless FOC (complete sensorless field oriented control) Proportional plus Integral block Low pass filter Differentiator and lag (high pass filter) Ramp Limit Angle estimate (sensorless control) Inverse Clark transformation Vector rotator Bit latch Peak detect Transition Multiply-divide (signed and unsigned) Adder Divide (signed and unsigned) 8051 microcontroller Two 16 bit timer/counters One 16 bit periodic timer One 16 bit watchdog timer One 16 bit capture timer Up to 14 discrete digital I/Os Seven-channel 12 bit A/D o Buffered (current sensing) two channels (0 – 1.2V input) o Unbuffered five channels (0 – 1.2V input) JTAG port (4 pins) Up to two channels of analog output (8 bit PWM) UART I 2C/SPI port 2K byte data RAM |
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