8XC196KB8XC196KB16

Symbol

Name and Function

Port 0

8-bit high impedance input-only port Three pins can be used as digital inputs andor as

analog inputs to the on-chip AD converter

Port 1

8-bit quasi-bidirectional IO port These pins are shared with HOLD HLDA and BREQ

Port 2

8-bit multi-functional port All of its pins are shared with other functions in the 87C196KB

Pins P26 and P27 are quasi-bidirectional

Ports 3 and 4

8-bit bidirectional IO ports with open drain outputs These pins are shared with the

multiplexed addressdata bus which has strong internal pullups

HOLD

Bus Hold input requesting control of the bus Enabled by setting WSR7

HLDA

Bus Hold acknowledge output indicating release of the bus Enabled by setting WSR7

BREQ

Bus Request output activated when the bus controller has a pending external memory

cycle Enabled by setting WSR7

TxD

The TxD pin is used for serial port transmission in Modes 1 2 and 3 In Mode 0 the pin is

used as the serial clock output

RxD

Serial Port Receive pin used for serial port reception In Mode 0 the pin functions as input or

output data

EXTINT

A rising edge on the EXTINT pin will generate an external interrupt

T2CLK

The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input

T2RST

A rising edge on the T2RST pin will reset Timer2

PWM

The pulse width modulator output

T2UP-DN

The T2UPDN pin controls the direction of Timer2 as an up or down counter

T2CAPTURE

A rising edge on P27 will capture the value of Timer2 in the T2CAPTURE register

PMODE

Programming Mode Select Determines the EPROM programming algorithm that is

performed PMODE is sampled after a chip reset and should be static while the part is

operating

SID

Slave ID Number Used to assign each slave a pin of Port 3 or 4 to use for passing

programming verification acknowledgement

PALE

Programming ALE Input Accepted by the 87C196KB when it is in Slave Programming

Mode Used to indicate that Ports 3 and 4 contain a commandaddress

PROG

Programming Falling edge indicates valid data on PBUS and the beginning of

programming Rising edge indicates end of programming

PACT

Programming Active Used in the Auto Programming Mode to indicate when programming

activity is complete

PVAL

Program Valid This signal indicates the success or failure of programming in the Auto

Programming Mode A zero indicates successful programming

PVER

Program Verification Used in Slave Programming and Auto CLB Programming Modes

Signal is low after rising edge of PROG if the programming was not successful

AINC

Auto Increment Active low signal indicates that the auto increment mode is enabled Auto

Increment will allow reading or writing of sequential EPROM locations without address

transactions across the PBUS for each read or write

Ports 3

AddressCommandData Bus Used to pass commands addresses and data to and from

slave mode 87C196KBs Used by chips in Auto Programming Mode to pass command

and 4

addresses and data to slaves Also used in the Auto Programming Mode as a regular

(Programming

Mode)

programming mode

7