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VSP2000 Datasheet(PDF) 3 Page - Burr-Brown (TI) |
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VSP2000 Datasheet(HTML) 3 Page - Burr-Brown (TI) |
3 / 12 page ® VSP2000 3 +VS ....................................................................................................... +6V Analog Input ......................................................... (0 –0.3V) to (+VS +0.3V) Logic Input ........................................................... (0 –0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100 °C Junction Temperature .................................................................... +150 °C Storage Temperature ..................................................................... +150 °C ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER(1) RANGE VSP2000 48-Lead LQFP 340 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION 27 CCD R Capacitor for Dummy Feedback Loop 28 AVSS2 Analog Ground 29 AGC1 Sets Gain of CCD Channel, 1k Ω Resistor 30 AGC2 Sets Gain of CCD Channel, 16k Ω Resistor 31 AVSS3 Analog Ground 32 LCM Attenuator Common-Mode Bypass 33 AVDD1 Analog +Supply 34 INT BIAS 2 Internal Bias, should be connected to GND with 0.1 µF Capacitor 35 AVSS Analog Ground 36 INT BIAS 1 Internal Bias, should be connected to GND with 0.1 µF Capacitor 37 2.4V Attenuator Ladder Bypass 38 CM ADS Common-Mode Voltage 39 AVDD2 Analog +Supply 40 AVDD3 Analog +Supply 41 DVSS Digital Ground 42 AVDD Analog +Supply 43 AVDD4 Analog +Supply 44 AVDD5 Analog +Supply 45 AVSS4 Analog Ground 46 AVSS5 Analog Ground 47 REFN ADS –Reference, Bypass to Ground 48 REFP ADS +Reference, Bypass to Ground 1DVSS1 Digital Ground 2 B10 (LSB) LSB of ADS 3 B9 Bit 9 4 B8 Bit 8 5 B7 Bit 7 6 B6 Bit 6 7 B5 Bit 5 8 B4 Bit 4 9 B3 Bit 3 10 B2 Bit 2 11 B1 (MSB) MSB of ADS 12 DRVDD Digital +Supply of ADS Output 13 DRVSS Digital Ground for ADS Output 14 DVSS2 Digital Ground 15 DVSS3 Digital Ground 16 ADCK ADS Clock, Data Output on Falling Edge 17 DVDD1 Digital +Supply 18 PD L = Normal Operation, H = Reduced Power 19 PB L = –FS + 32 LSB, H = Normal at CCD Mode 20 OB Optical Black Clamp Pulse, Active LOW 21 REFCK Neg Pulse, Trailing Edge Samples Reset 22 DATCK Neg Pulse, Trailing Edge Samples Data 23 DUMC Dummy Clamp, Active LOW 24 C Capacitor for Optical Feedback 25 AVSS1 Analog Ground 26 CCD D CCD Signal Input PIN CONFIGURATION PIN DESIGNATOR DESCRIPTION PIN DESIGNATOR DESCRIPTION PIN DESCRIPTIONS 36 35 34 33 32 31 30 29 28 27 26 25 INT BIAS1 AV SS INT BIAS2 AV DD1 LCM AV SS3 AGC2 AGC1 AV SS2 CCD R CCD D AV SS1 1 2 3 4 5 6 7 8 9 10 11 12 DV SS1 B10 (LSB) B9 B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DRV DD 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 VSP2000 |
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