®

8

PLL1700

FIGURE 8. Software Mode Control Format.

FS1

FS0

SAMPLING FREQUENCY

DEFAULT

0

0

48kHz

O

0

1

44.1kHz

1

0

32kHz

1

1

Reserved

PROGRAM REGISTER BIT-MAPPING

The built-in functions of the PLL1700 are controlled through

a 16-bit program register. This register is loaded using MD.

After the 16 data bits are clocked in using the rising edge of

MC, ML is used to latch the data into the register. Table V

shows the bit-mapping of the registers. The software mode

control format and control data input timing is shown in

Figures 8 and 9, respectively.

Mode Register

CE [1:6]:

Clock Output Control

DESCRIPTION

SYMBOL

MIN

TYP

MAX

UNITS

MC Pulse Cycle Time

100

ns

MC Pulse Width LOW

40

ns

MC Pulse Width HIGH

40

ns

MD Hold Time

40

ns

MD Set-Up Time

40

ns

ML Low Level Time

16

ML High Level Time

200

ns

40

ns

40

ns

NOTES: (1) MC clocks: MC clock period. (2) MC rising edge for LSB to ML rising edge. (3) ML rising edge

to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted.

FIGURE 9. Control Data Input Timing.

REGISTER

BIT NAME

DESCRIPTION

MODE

CE6

MCKO Output Enable/Disable

CE5

MCKO Output Enable/Disable

CE4

SCKO4 Output Enable/Disable

CE3

SCKO3 OUtput Enable/Disable

CE2

SCKO2 Output Enable/Disable

CE1

SCKO1 Output Enable/Disable

SR [1:0]

Sampling Rate Select

FS [1:0]

Sampling Frequency Select

TABLE V. Register Mapping.

Mode Register

FS [1:0]:

Sampling Frequency Group Select

SR [1:0]:

Sample Rate Select

SR1

SR0

SAMPLING RATE

DEFAULT

0

0

Standard

O

0

1

Double

1

0

Reserved

1

1

Reserved

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ML (pin 1)

MC (pin 20)

MD (pin 19)

D15 D14 D13 D12 D11 D0 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

1

1

0

0

CE6 CE5 CE4 CE3 CE2 CE1 SR1 SR0 FS1 FS0

CE1 - CE6

CLOCK OUTPUT CONTROL

DEFAULT

0

Clock Output Disable

1

Clock Output Enable

O

MSB

LSB

1.4V

1.4V

1.4V

t

MLS

t

MCH

t

MCL

t

MLL

t

MHH

t

MLH

t

MLS

t

MDS

t

MDH

t

MCY

ML (pin 1)

MC (pin 20)

MD (pin 19)