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PCM1760 Datasheet(PDF) 9 Page - Burr-Brown (TI) |
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PCM1760 Datasheet(HTML) 9 Page - Burr-Brown (TI) |
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9 / 15 page  ® 9 PCM1760P/U DF1760P/U T PCF T CSV CAL SDATA /PD T PSF T PDW T PCR DESCRIPTION NAME MIN TYP MAX UNITS Pulse Width of /PD Input T PDW 2 – – 1/Fclk Delay from /PD Input to CAL Output T PCR – – 6 1/Fclk Calibration Cycle Duration T PCF – 4096 – 1/fs Delay from /PD Input to S DATA LTPSF – – 6 1/Fclk Delay from Completion of Calibration to SDATA Valid T CSV – 1 – 1/fs FIGURE 3b. DF1760 Power Down and Offset Calibration. SYSTEM CLOCK: 256fs DESCRIPTION NAME MIN TYP MAX UNITS Low Level Duration T CLKL 31 – – ns High Level Duration T CLKH 31 – – ns T CLKH T CLKL 2.0V 1.4V 0.8V T LH T HL DESCRIPTION NAME MIN TYP MAX UNITS SCLK Frequency F SLK 32fs 48fs 64fs – Low Duration of FSCLK T SLKL 100 – – ns High Duration of FSCLK T SLKH 100 – – ns Delay from SCLK to L/R Edge T SLR –70 – 70 ns Delay from Falling Edge of SCLK to SDATA Valid T DSS –– 50 ns Delay from SCLK to FSYNC Edge T SF –70 – 0 ns Delay from Rising Edge of SCLK to SDATA Valid T DSV 100 – – ns Delay from SDATA Valid to Rising Edge of SCLK T SDR 100 – – ns SCKL SDATA L/R FSYNC T SLR T SDR T SF T DSS T DSV T SLKH TSLKL FIGURE 3e. Timing of Slave Mode, DF1760. FIGURE 3f. Power On and Mode Reset Timing. APPLIES TO DESCRIPTION NAME MIN TYP MAX UNITS(1) MODE Power on to PD ↑ T PDW 2 1/fs Master/Slave PD ↑ to L/R ↑ T SP –1 +1 1/Fclk Slave (LRSC = “H”) PD ↑ to L/R ↓ T SP –1 +1 1/Fclk Slave (LRSC = “L”) NOTE: (1) fs: sampling rate. Fclk: system clock frequency. T PDW T PDW T SP T SP Power L/R PD <LRSC = “H” T PDW T PDW T SP T SP Power L/R PD <LRSC = “L” SYSTEM CLOCK: 384fs DESCRIPTION NAME MIN TYP MAX UNITS Low Level Duration T CLKL 24 – – ns High Level Duration T CLKH 24 – – ns Rise Time T LH –– 6 ns Fall Time T HL –– 6 ns FIGURE 3c. System Clock Timing Requirements of DF1760. T SDR T SF T DSS SCLK SDATA L/R FSYNC T SLR T DSV T DSS T DSV T SF DESCRIPTION NAME MIN TYP MAX UNITS SCLK Frequency F SLK – 64fs – SCLK Frequency Duty Cycle – 50 – % FSYNC Frequency F SYNC – 2fs – FSYNC Frequency Duty Cycle – 50 – % Delay from SCLK to L/R Edge T SLR –20 – 50 ns Delay from Falling Edge of SCLK to SDATA Valid T DSS –– 50 ns Delay from SCLK to FSYNC Edge T SF –20 – 50 ns Delay from Rising Edge of SCLK to SDATA Valid T SDR 100 – – ns Delay from SDATA Valid to Rising Edge of SCLK T DSV 100 – – ns FIGURE 3d. Output Timing of Master Mode, DF1760. |
Similar Part No. - PCM1760 |
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Similar Description - PCM1760 |
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