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SN54LS166J Datasheet(PDF) 1 Page - Motorola, Inc |
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SN54LS166J Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 4 page 5-1 FAST AND LS TTL DATA 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. • Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion 14 13 12 11 10 9 1 2 3 4 5 6 7 16 15 8 VCC SERIAL INPUT SHIFT/ LOAD H QH G E F CLEAR A B C D CLOCK INHIBIT CLOCK GND PARALLEL PARALLEL INPUTS INPUT OUTPUT PARALLEL INPUTS SHIFT/ LOAD SERIAL INPUT CLOCK INHIBIT H QH G F E A B C D CK CLEAR FUNCTION TABLE INPUTS INTERNAL OUTPUTS OUTPUT QH CLEAR SHIFT/ LOAD CLOCK INHIBIT CLOCK SERIAL PARALLEL INTERNAL OUTPUTS OUTPUT QH CLEAR SHIFT/ LOAD CLOCK INHIBIT CLOCK SERIAL A . . . H QA QB QH L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L ↑ X a . . . h a b h H H L ↑ H X H QAn QGn H H L ↑ L X L QAn QGn H X H ↑ X X QA0 QB0 QH0 SN54/74LS166 8-BIT SHIFT REGISTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC 16 1 D SUFFIX SOIC CASE 751B-03 |
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