10

®

DAC7624/7625

ANALOG OUTPUTS

fier can swing to within 2.25V of the supply rails, guaran-

teed over the –40

°C to +85°C temperature range. With V

SS

= 0V (single-supply operation), the output can swing to

ground. Note that the settling time of the output op-amp will

be longer with voltages very near ground. Also, care must be

Since the output voltage cannot swing below ground, the

output voltage may not change for the first few digital input

negative offset.

The behavior of the output amplifier can be critical in some

applications. Under short circuit conditions (DAC output

shorted to ground), the output amplifier can sink a great deal

more current than it can source. See the specification table

for more details concerning short circuit current.

REFERENCE INPUTS

(essentially, the offset of the output op-amp). The maximum

connected to ground or must be in the range of –4.75V to

tions, the bias values may be in error and proper operation

of the device is not guaranteed.

voltages and can vary from a few microamps to approxi-

to sink current, only source it. Bypassing the reference

voltage or voltages with at least a 0.1uF capacitor placed as

close to the DAC7624/25 package is strongly recommended.

DIGITAL INTERFACE

Table I shows the basic control logic for the DAC7624/25.

Note that each internal register is level triggered and not

edge triggered. When the appropriate signal is LOW, the

register becomes transparent. When this signal is returned

HIGH, the digital word currently in the register is latched.

The first set of registers (the Input Registers) are triggered

via the A0, A1, R/W, and CS inputs. Only one of these

registers is transparent at any given time. The second set of

registers (the DAC Registers) are all transparent when LDAC

input is pulled LOW.

Each DAC can be updated independently by writing to the

appropriate Input Register and then updating the DAC

Register. Alternatively, the entire DAC Register set can be

configured as always transparent by keeping LDAC LOW—

the DAC update will occur when the Input Register is

written.

The double buffered architecture is mainly designed so that

each DAC Input Register can be written at any time and then

all DAC voltages updated simultaneously by pulling LDAC

LOW. It also allows a DAC Input Register to be written to

at any point and the DAC voltage to be synchronously

changed via a trigger signal connected to LDAC.

STATE OF

SELECTED

SELECTED

STATE OF

INPUT

INPUT

ALL DAC

A1

A0

R/W

CS

RESET

LDAC

REGISTER

REGISTER

REGISTERS

LLL

L

A

Transparent

Transparent

L

H

L

L

H

L

B

Transparent

Transparent

H

L

L

L

H

L

C

Transparent

Transparent

H

H

L

L

H

L

D

Transparent

Transparent

LLLL

H

H

A

Transparent

Latched

L

H

L

L

H

H

B

Transparent

Latched

H

L

L

L

H

H

C

Transparent

Latched

H

H

L

L

H

H

D

Transparent

Latched

L

L

H

L

H

H

A

Readback

Latched

L

H

H

L

H

H

B

Readback

Latched

H

L

H

L

H

H

C

Readback

Latched

H

H

H

L

H

H

D

Readback

Latched

X

X

H

H

L

NONE

(All Latched)

Transparent

X

X

X

H

H

H

NONE

(All Latched)

Latched

XXXX

L

X

ALL

are in their latched state retain the reset value.

TABLE I. DAC7624 and DAC7625 Control Logic Truth Table.