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ADS931 Datasheet(PDF) 2 Page - Burr-Brown (TI) |
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ADS931 Datasheet(HTML) 2 Page - Burr-Brown (TI) |
2 / 12 page 2 ® ADS931 SPECIFICATIONS At TA = full specified temperature range unless otherwise noted. +VS = LVDD = +3V, specified single-ended input (1V to 2V) and sampling rate = 30MHz, unless otherwise specified. The input range is 2.25V to 3.25V when specified for +5V operation. ADS931E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 8 Bits SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C ANALOG INPUT Specified Full Scale Input Range(1) 1Vp-p +1.0 +2.0 V Common-mode Voltage +1.5 V Analog Input Bias Current 1 µA Input Impedance 1.25 || 5 M Ω || pF DIGITAL INPUTS Logic Family TTL/HCT Compatible CMOS High Input Voltage, VIH +2.0 LVDD V Low Input Voltage, VIL +0.8 V High Input Current, IIH ±10 µA Low Input Current, IIL ±10 µA Input Capacitance 5pF CONVERSION CHARACTERISTICS Start Conversion Rising Edge of Convert Clock Sample Rate 10k 30M Samples/s Data Latency 5 Clk Cycles DYNAMIC CHARACTERISTICS Differential Linearity Error VS = +3V and +5V f = 500MHz ±0.7 ±1.0 LSB f = 12.5MHz ±0.7 LSB No Missing Codes VS = +3V and +5V Guaranteed Integral Nonlinearity Error, f = 500kHz VS = +3V and +5V ±1.0 ±2.5 LSB Spurious Free Dynamic Range(2) VS = +3V and +5V f = 500kHz (–1dBFS input) 49 dBFS(3) f = 12.5MHz (–1dBFS input) 43 49 dBFS Two-Tone Intermodulation Distortion(4) f = 3.6MHz and 3.5MHz (–7dBFS each tone) 54 dBFS Signal-to-Noise Ratio (SNR) VS = +3V and +5V f = 500kHz (–1dBFS input) 48 dB f = 12.5MHz (–1dBFS input) 44 48 dB Signal-to-(Noise + Distortion) (SINAD) VS = +3V and +5V f = 500kHz (–1dBFS input) 45 dB f = 12.5MHz (–1dBFS input) 40 45 dB Effective Number of Bits f = 12MHz(5) 7.2 Bits Differential Gain Error NTSC, PAL 2.3 % Differential Phase Error NTSC, PAL 1 degrees Output Noise Input AC-Grounded 0.2 LSBs rms Aperture Delay Time 2ns Aperture Jitter 7 ps rms Analog Input Bandwidth Small Signal –20dBFS Input 350 MHz Full Power 0dBFS Input 100 MHz Overvoltage Recovery Time(6) 2ns DIGITAL OUTPUTS CL = 15pF Logic Family TTL/HCT Compatible CMOS Logic Coding Straight Offset Binary High Output Voltage, VOH 2.4 VDD V Low Output Voltage, VOL 0.4 V 3-State Enable Time OE = L 20 40 ns 3-State Disable Time OE = H 2 10 ns Internal Pull-Down 50 k Ω Power-Down Enable Time Pwrdn = L 133 ns Power-Down Disable Time Pwrdn = H 18 ns Internal Pull-Down 50 k Ω ACCURACY VS = +3V and +5V Gain Error 2.4 3.5 %FS Input Offset(7) Referred to Ideal Midscale ±6.5 ±25 mV Power Supply Rejection (Gain) ∆ V S = +10% 42 75 dB External REFT Voltage Range REFB +0.5 2 VS–0.8 V External REFB Voltage Range 0.8 1 REFT –0.5 V Reference Input Resistance 4k Ω |
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