5

8707B–SEEPR–3/10

AT25010B/020B/040B

Note:

1. This parameter is characterized and is not 100% tested.

2.

Serial Interface Description

MASTER: The device that generates the serial clock.

SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010B/020B/040B always operates as a

slave.

TRANSMITTER/RECEIVER: The AT25010B/020B/040B has separate pins designated for data transmission (SO)

and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte con-

tains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both

the read and write instructions.

INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010B/020B/040B, and

the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This

will reinitialize the serial communication.

CHIP SELECT: The AT25010B/020B/040B is selected when the CS pin is low. When the device is not selected,

data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state.

HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010B/020B/040B. When the device

is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the

master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK

pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still

toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.

WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the

WP pin is brought low, all write operations are inhibited.

WP going low while CS is still low will interrupt a write to the AT25010B/020B/040B. If the internal write cycle has

already been initiated, WP going low will have no effect on any write operation.

t

HZ

Hold to Output High Z

4.5

− 5.5

2.5

− 5.5

1.8

− 5.5

25

50

100

ns

t

DIS

Output Disable Time

4.5

− 5.5

2.5

− 5.5

1.8

− 5.5

25

50

100

ns

t

WC

Write Cycle Time

4.5

− 5.5

2.5

− 5.5

1.8

− 5.5

5

5

5

ms

Endurance(1)

5.0V, 25

⋅C, Page Mode

1M

Write Cycles

Table 1-3.

AC Characteristics (Continued)

Applicable over recommended operating range from T

CL = 1 TTL Gate and 30 pF (unless otherwise noted)

Symbol

Parameter

Voltage

Min

Max

Units