2

®

ADS7819

9

FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).

t

9

Hi-Z State

t

8

BUSY

R/C

DATA BUS

MODE

Acquire

Data Valid

t

10

Data Valid

Hi-Z State

Convert

Convert

t

7

t

6

t

3

t

4

t

1

t

2

t

5

Acquire

t

12

FIGURE 3. Using CS to Control Conversion and Read Timing.

t

9

Hi-Z State

BUSY

R/C

CS

DATA

BUS

MODE

Acquire

Data Valid

Hi-Z State

Convert

t

7

t

2

t

6

t

3

t

4

t

11

t

5

Acquire

t

13

t

11

t

1

t

11

t

11

FIGURE 4a. Circuit Diagram With External Hardware Trim.

NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim

gain at 2.5V.

50

Ω

AGND2

CAP

REF

AGND1

V

IN

+

0.1µF

10µF

V

IN

+5V

R

1

20k

Ω

P

1

5k

Ω

P

2

5k

Ω

R

2

604k

Ω

–5V

+5V

FIGURE 4b. Circuit Diagram Without External Hardware

Trim.

50

Ω

AGND2

CAP

REF

AGND1

V

IN

+

0.1µF

10µF

V

IN