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ADS7819P Datasheet(PDF) 4 Page - Burr-Brown (TI) |
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ADS7819P Datasheet(HTML) 4 Page - Burr-Brown (TI) |
4 / 11 page 4 ® ADS7819 PIN CONFIGURATION V IN AGND1 REF CAP AGND2 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 DGND +V ANA +V DIG –V ANA BUSY CS R/C DGND +V DIG +V ANA NC(1) D0 (LSB) D1 D2 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS7819 NOTE: (1) Not Internally Connected. PIN ASSIGNMENTS DIGITAL PIN # NAME I/O DESCRIPTION 1VIN Analog Input. Connect via 50 Ω to analog input. Full-scale input range is ±2.5V. 2 AGND1 Analog Ground. Used internally as ground reference point. Minimal current flow. 3 REF Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both cases, decouple to ground with a 0.1 µF ceramic capacitor. 4 CAP Reference Buffer Output. 10 µF tantalum capacitor to ground. Nominally +2V. 5 AGND2 Analog Ground. 6 D11 (MSB) O Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 7 D10 O Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 8 D9 O Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 9 D8 O Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 10 D7 O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 11 D6 O Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 12 D5 O Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 13 D4 O Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 14 DGND Digital Ground. 15 D3 O Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 16 D2 O Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 17 D1 O Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 18 D0 (LSB) O Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress. 19 Not internally connected. 20 +VANA Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28. 21 +VDIG Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28. 22 DGND Digital ground. 23 R/C I Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output data bits. 24 CS I Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH and no conversion in progress, a falling edge on CS will enable the output data bits. 25 BUSY O Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. 26 –VANA Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1 µF ceramic and 10µF tantalum capacitors. 27 +VDIG Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28. 28 +VANA Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground with 0.1 µF ceramic and 10µF tantalum capacitors. |
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