®

7

ADS7800

FIGURE 2. Basic

±10V Operation.

OPERATION

BASIC OPERATION

Figure 2 shows the simple hookup circuit required to operate

the ADS7800 in a

±10V range in the Convert Mode. A

convert command arriving on pin 19, R/C, (a pulse taking

pin 19 LOW for a minimum of 40ns) puts the ADS7800 in

the hold mode, and a conversion is started. Pin 21, BUSY,

will be held LOW during the conversion, and rises only after

the conversion is completed and the data has been trans-

ferred to the output latches. Thus, the rising edge of the

signal on pin 21 can be used to read the data from the

conversion. Also, during conversion, the BUSY signal puts

the output data lines in Hi-Z states and inhibits input lines.

This means that pulses on pin 19 are ignored, so that new

conversions cannot be initiated during a conversion, either

as a result of spurious signals or to short-cycle the

ADS7800.

In the Read Mode, the input to pin 19 is kept normally LOW,

and a HIGH pulse is used to read data and initiate a

conversion. In this mode, the rising edge of R/C on pin 19

will enable the output data pins, and the data from the

previous conversion becomes valid. The falling edge then

puts the ADS7800 in a hold mode, and initiates a new

conversion.

The ADS7800 will begin acquiring a new sample as soon

as the conversion is completed, even before the BUSY

output rises on pin 21, and will track the input signal until

the next conversion is started, whether in the Convert Mode

or the Read Mode.

THEORY OF OPERATION

The ADS7800 combines the advantages of advanced CMOS

technology (logic density, stable capacitors, and good

analog switches) with Burr-Brown’s proven skills in laser-

trimmed thin-film resistors to provide a complete sampling

A/D converter.

A basic charge-redistribution successive approximation

architecture converts analog input voltages into digital

words. Figure 1 shows the operation of a simplified three

bit charge redistribution A/D. Precision laser-trimmed

scaling resistors at the input divide standard input ranges

(

±10V or ±5V for the ADS7800) into levels compatible with

the CMOS characteristics of the internal capacitor array.

While in the sampling mode, the capacitor array switch for

on the MSB capacitor is proportional to the voltage level of

and S

offset from the reference source REF. At the same time,

switch S

offset errors in the CMOS comparator.

to trap a charge on the MSB capacitor proportional to the

input level at the time of the sampling command, switches

S

trapped on the capacitor array can now be moved between

the three capacitors in the array by connecting switches S

connect to GND) successively, changing the voltage gener-

ated at the comparator input node.

The first approximation connects the MSB capacitor via

to GND. Depending on whether the comparator output is

or “G”, and moves on to make the next approximation by

successive approximation steps are made for this simple

converter, the voltage level at the comparator will be within

1/2LSB of GND, and the data output word will be based on

FIGURE 1. 3-Bit Charge Redistribution A/D.

G

R

S

G

R

G

R

+

–

L

o

g

i

c

Comparator

Out

To Switches

Ref

Signal

Input

4C

2C

C

IN 1

IN 2

REF

AGND

D11 (MSB)

D10

D9

D8

D7

D6

D5

D4

+5V

+5V

–15V

BUSY

CS

R/C

HBE

D0 (LSB)

D1

D2

D3

DGND

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

+

47µF

Input

Convert

Command

Busy

+

–15V

+

1µF

+5V

6.8µF

0.1µF

D11

(MSB)

D0

(LSB)

Data Out