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BQ24261RGET Datasheet(PDF) 11 Page - Texas Instruments |
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BQ24261RGET Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 46 page  bq24260 bq24261 bq24262A www.ti.com SLUSBU4A – DECEMBER 2013 – REVISED JANUARY 2014 Pin Configurations PIN NUMBER PIN NUMBER PIN bq24260 bq24261/2 I/O DESCRIPTION NAME YFF RGE YFF RGE AGND F1 12, 20 F1 12, 20 Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. BAT Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at F3-F6 8, 9 F3-F6 8, 9 I/O least 1 μF of ceramic capacitance. See Applicaton section for additional details. BGATE External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a very low resistance discharge path. Connect BGATE to the gate of the external F2 11 F2 11 O MOSFET. BGATE is low during high impedance mode or when no input is connected. If no external FET is required, leave BGATE disconnected. Do not connect BGATE to GND. BOOT High Side MOSFET Gate Driver Supply. Connect 0.033µF of ceramic capacitance (voltage C6 2 C6 2 I rating > 10V) from BOOT to SW to supply the gate drive for the high side MOSFET. CD IC Hardware Disable Input. Drive CD high to place the bq24260 in high-z mode. Drive CD low C5 4 C5 4 I for normal operation. CD is pulled low internally with 100k Ω D+ D4 14 – – I D+ and D– Connections for USB Input Adapter Detection. When a source is initially connected to the input during DEFAULT mode, and a short is detected between D+ and D–, the input D– D3 15 – – I current limit is set to 1.5A. If a short is not detected, the USB100 mode is selected. DRV Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND with at least 1 μF of ceramic capacitance. DRV may be used to drive external D6 3 D6 3 O loads up to 10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP). IN DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). C1-C4 19 C1-C4 19 I Bypass IN to PGND with at least a 4.7 μF of ceramic capacitance. INT Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during charging. INT is high impedance when charging is complete, disabled or the E2 10 E2 10 O charger is in high impedance mode. When a fault occurs, a 128 μs pulse is sent out as an interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through a 100k Ω resistor to communicate with the host processor. PGND A1-A6 21,22 A1-A6 21,22 – Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. PMID High Side Bypass Connection. Connect at least 1µF of ceramic capacitance from PMID to B1 1 B1 1 I PGND as close to the PMID and PGND pins as possible. PSEL Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit. Drive – – D4 14 I PSEL high to select USB100 (bq24261) or USB500 (bq24262A) mode, drive PSEL low to select 1.5A mode. SCL D2 16 D2 16 I I2C Interface Clock. Connect SCL to the logic rail through a 10k Ω resistor. SDA D1 17 D1 17 I/O I2C Interface Data. Connect SDA to the logic rail through a 10k Ω resistor. STAT Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low during charging. STAT is high impedance when charging is complete, disabled or the charger is high impedance mode. When a fault occurs, a 128 μs pulse is sent out as an E1 13 E1 13 O interrupt for the host. STAT is enabled /disabled using the EN_STAT bit in the control register. Connect STAT to a logic rail using an LED for visual indication or through a 100k Ω resistor to communicate with the host processor. SW Inductor Connection. Connect to the switched side of the external inductor. The inductance B2-B6 23, 24 B2-B6 23, 24 O must be between 1.5µH and 2.2µH. SYS System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with at least 10 μF of ceramic capacitance. The SYS E3-E6 6, 7 E3-E6 6, 7 I rail must have at least 20µF of total capacitance for stable operation. See Application section for additional details. TS Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA D5 5 D5 5 I compatibility. TS faults are reported by the I2C interface. Pull TS high to VDRV to disable the TS function if unused. See the NTC Monitor section for more details on operation and selecting the resistor values. Thermal There is an internal electrical connection between the exposed thermal pad and the PGND pin PAD of the device. The thermal pad must be connected to the same potential as the PGND pin on – – – – – the printed circuit board. Do not use the thermal pad as the primary ground input for the device. PGND pin must be connected to ground at all times. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: bq24260 bq24261 bq24262A |
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