5-177

FAST AND LS TTL DATA

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct

Clear and Clock Pulse inputs. Output changes are initiated by the

HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the

other inputs and makes the Q output LOW.

The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner

power pins.

NOTE:

The Flatpak version has the

same pinouts (Connection

Diagram) as the Dual In-Line

Package.

CONNECTION DIAGRAM DIP (TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

VCC

8

7

GND

CD1 CP1 K2

CD2 CP2

J2

Q2

Q2

K1

Q1

Q1

J1

LOGIC SYMBOL

VCC = PIN 14

GND = PIN 7

1

1

12

4

3

2

13

J

Q

CP

K

Q

CD

2

8

9

11

5

6

J

Q

CP

K

Q

CD

10

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

TA

Operating Ambient Temperature Range

54

74

– 55

0

25

25

125

70

°C

IOH

Output Current — High

54, 74

– 0.4

mA

IOL

Output Current — Low

54

74

4.0

8.0

mA

SN54/74LS107A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

14

1

D SUFFIX

SOIC

CASE 751A-02