LMH0040, LMH0050

LMH0070, LMH0340

SNLS271I – APRIL 2007 – REVISED APRIL 2013

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LVDS DATA ORDER

When serializing the data, the data bit latched in on TX0 is output first, followed by TX1, TX2, TX3 and then TX4.

If starting with a 10 bit word, T0..T9, with T0 being the LSB, and it is desired that this be serialized such that the

LSB is sent out first, then the least significant 5 bit word would be provided to the serializer first, followed by the

most significant word, and the resulting serialized output would have the LSB being sent first, and the 10 bit MSB

(T9) would be transmitted last. If it is desired to reverse the serialization order, such that the bit presented on

TX4 is output first, this mode of operation may be selected via register 0x2E'h.

LOOP FILTER

The SER has an internal PLL which is used to generate the serialization clock from the parallel clock input. The

loop filter for this PLL is external, and for optimum results in Serial Digital Interface applications, a capacitor and

a resistor in series should be connected between pins 26 and 27. Recommended value for the capacitor is

0.1

μF. Recommended value for the resistor is 500 Ω.

PLL FILTER / BYPASS

The SER has an external filter capacitor for the PLL. The recommended value for this capacitor is 22

μF with a

connection to the 3.3V rail.

DVB_ASI MODE

The SER has a special mode for DVB-ASI. In this mode, the input signal on TX4± is treated as a data valid bit, if

high, then the four bit nibbles from TX0-TX3 are taken to form an 8 bit word, which is then converted to a 10 bit

code via an internal 8b10b encoder and this 10 bit word is serialized and driven on the output. The nibble taken

in on the rising edge of the clock is the most significant nibble and the nibble taken in on the falling edge is the

least significant nibble. If TX4± is low, then the input on TX0-TX3 are ignored and the 10b idle character is

inserted in the output stream. The Idle character can be reprogrammed to be any 10 bit code desired via

registers 0x11'h and 0x12'h.

SDI OUTPUT INTERFACING

The serial outputs provide low-skew complimentary or differential signals. The output buffer is a current mode

design, with a high impedance output. To drive a 75

Ω transmission line connect a 75Ω resistor from each of the

output pins to 2.5V. This resistor has two functions – it converts the current output to a voltage, which is used to

drive the cable, and it acts as the back termination resistor for the transmission line. The resistor should be

placed as close to the output pin as is practicable. The output driver automatically adjusts its slew rate depending

on the input datarate so that it will be in compliance with SMPTE 259M, SMPTE292M or SMPTE 424M as

appropriate. In addition to output amplitude and rise/fall time specifications, the SMPTE specs require that SDI

outputs meet an Output Return Loss (ORL) specification. There are parasitic capacitances that will be present

both at the output pin of the device and on the application printed circuit board. To optimize the return loss

implement a series network comprised of a parallel inductor and resistor. The actual values for these

components will vary from application to application, but the typical interface circuit shows values that would be a

good starting point. Figure 6 shows an equivalent output circuit for the LMH0340 / LMH0040 / LMH0070. The

collectors present a high impedance current source. The external 75

Ω resistors will provide the back termination

resistance as well as converting the current to a voltage – with the addition of the termination resistance at the

load, there will be an overall output resistance of 37.5

Ω, which in conjunction with the 24mA current source will

develop the 800mV swings called for in the standard.

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