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W181-53G Datasheet(PDF) 2 Page - Cypress Semiconductor |
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W181-53G Datasheet(HTML) 2 Page - Cypress Semiconductor |
2 / 9 page W181 Document #: 38-07152 Rev. *D Page 2 of 9 Key Specifications Supply Voltages: .........................................VDD = 3.3V ± 5% .................................................................or VDD = 5V ± 10% Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz Crystal Reference Range.................. 28 MHz ≤ Fin ≤ 40 MHz Cycle to Cycle Jitter: ....................................... 300 ps (max.) Selectable Spread Percentage: ................... 1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.) Overview The W181 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple imple- mentation. Functional Description The W181 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W181 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Pin Definitions Pin Name Pin No. (SOIC) Pin No. (TSSOP)(-01) Pin Type Pin Description CLKOUT 5 8 O Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock (SSON# asserted). CLKIN or X1 1 2 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 2 3 I Crystal Connection: If using an external reference, this pin must be left unconnected. SSON# 8(02/03/52/53) -- I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. FS1:2 7, 8 (01/51) 12, 1 I Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. SS% 4 6 I Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. VDD 6 10 P Power Connection: Connected to 3.3V or 5V power supply. GND 3 4 G Ground Connection: Connect all ground pins to the common system ground plane. NC 5, 7, 9, 11, 13, 14 NC No Connection Table 1. Modulation Width Selection SS% W181-01, 02, 03 Output W181-51, 52, 53 Output 0 –1.25% (Down Spread) ±0.625 (Center Spread) 1 –3.75% (Down Spread) ±1.875% (Center Spread) Table 2. Frequency Range Selection W181 Option# FS2 FS1 -01, 51 (MHz) -02, 52 (MHz) -03, 53 (MHz) 00 28 ≤ FIN ≤ 38 28 ≤ FIN ≤ 38 N/A 01 38 ≤ FIN ≤ 48 38 ≤ FIN ≤ 48 N/A 10 46 ≤ FIN ≤ 60 N/A 46 ≤ FIN ≤ 60 11 58 ≤ FIN ≤ 75 N/A 58 ≤ FIN ≤ 75 |
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